Methodology for Board Level Functional Simulation and Hardware/Software Co-Verification using Seamless

ABSTRACT

Less time to deliver these complex designs, the importance of delivering a first-time correct design and earlier hardware/software integration is becoming a priority in the product design cycle. One way to achieve the goal of a first-time correct hardware design is to use board level functional simulation. The Mentor Graphics Seamless® co-verification tool can be used in the board level simulation environment to perform hardware/software co-verification before the first physical prototype boards arrive in the lab. This not only provides earlier hardware/software integration testing, but also provides earlier and greater visibility of any problems that may arise during that integration.

This paper describes:

• The objectives of board level simulation and hardware/software co-verification
• A verification flow and verification environment using Seamless
• Different verification methodologies to address specific verification challenges
• Lessons learned
• Benefits derived and trade-offs from employing a board level functional simulation and hardware/software co-verification methodology using Seamless