Seamless Co-Verification of ARM Processor-based SoCs
White Paper
ABSTRACT
A long-standing collaboration between ARM and Mentor has produced an excellent silicon IP/EDA tool combination that has aided designers in successfully completing hundreds of SoC designs based on ARM processors. Read how the high-speed HW simulation capability increases productivity for verification and regression testing of complex SoC designs.Related Resources
FPGA Verification with Assertions: Why Bother? A...
White PaperFPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions
This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting...
TAGS: Avionics, COTS, SWaP, Thermal Characterization, Thermal Simulation, Questa Advanced Simulator
Advanced UVM Debugging
On-demand Web Seminar 47:58Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.
TAGS: Debugging, UVM, Questa Clock-Domain Crossing (CDC) Verification, Questa Formal Verification , Questa Codelink, Questa inFact, Questa Advanced Simulator, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification Management, Questa Verification IP
The 2012 Wilson Research Group Functional Verification...
On-demand Web Seminar 39:15The 2012 Wilson Research Group Functional Verification Study
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...
TAGS: Wilson Research Group Study, Questa Clock-Domain Crossing (CDC) Verification, Questa Formal Verification , Questa ADMS, Questa Codelink, Questa inFact, ModelSim, Questa Advanced Simulator, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification Management, Questa Verification IP

