To Retain or Not to Retain: How Do I Verify the State Elements of My Low Power Design?
Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.
The 2012 Wilson Research Group Functional Verification Study
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...
Off-line Debug of Multi-Core SoCs with Veloce Emulation
Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design...