Towards an Object-Oriented Design Methodology Using SystemVerilog
White Paper
ABSTRACT
Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are more and more seriously considering language-based methodologies for parts of their designs. The introduction of the System Verilog (SV) language initiated a closer relationship between software and hardware descriptions and development tools. This paper presents synthesis recommendations and the corresponding synthesis methodology to develop object-oriented models with SV constructs for hardware system implementations.Related Resources
Advanced UVM Debugging
On-demand Web Seminar 47:58Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.
TAGS: Debugging, UVM, Questa Clock-Domain Crossing (CDC) Verification, Questa Formal Verification , Questa Codelink, Questa inFact, Questa Advanced Simulator, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification Management, Questa Verification IP
The 2012 Wilson Research Group Functional Verification...
On-demand Web Seminar 39:15The 2012 Wilson Research Group Functional Verification Study
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...
TAGS: Wilson Research Group Study, Questa Clock-Domain Crossing (CDC) Verification, Questa Formal Verification , Questa ADMS, Questa Codelink, Questa inFact, ModelSim, Questa Advanced Simulator, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification Management, Questa Verification IP
Cookbook Recipes Beyond UVM: Effectively Modeling...
On-demand Web Seminar 42:28Cookbook Recipes Beyond UVM: Effectively Modeling and Analyzing Coverage
TAGS: Modeling, UVM, Questa Advanced Simulator, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification Management, Questa Verification IP