Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation
Veloce System-Level Power Analysis and Verification
Power analysis and verification need to move to the system level, improving upon and extending the capabilities and scope of RTL and gate-level techniques. The performance, capacity, and flexibility of...
Off-line Debug of Multi-Core SoCs with Veloce Emulation
Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design...
Virtual Devices for Protocol-Specific Host and Peripheral Interfaces
This paper provides a brief genealogy of virtual devices, describes their characteristics and benefits, and presents two design applications that demonstrate its utility and effectiveness.