Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation

ABSTRACT

Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification and validation platforms have been developed as separate flows, preventing reuse of modules and methods between the two. As a consequence, various customized verification and validation platform features must be devised and implemented to verify complex, highly integrated System on Chip (SoC) designs. Bringing these two flows together would save an immense amount of duplicate effort and time while potentially reducing the introduction of errors, since less code needs to be developed and maintained.