Virtual Devices for Protocol-Specific Host and Peripheral Interfaces
White Paper
ABSTRACT
This paper provides a brief genealogy of virtual devices, describes their characteristics and benefits, and presents two design applications that demonstrate its utility and effectiveness.
Virtualization makes emulation more readily available to all design teams within a company and increases the flexibility, visibility, and capacity of emulation environments. Virtualized solutions add a range of capabilities that promise to redraw the functional verification landscape. These include virtual host and peripheral models (called “virtual devices”) and software debug technologies enabled by transaction-based, co-model channel technology. Virtual devices are an emerging technology, with products beginning to offer the same functionality as traditional In-Circuit (ICE) solutions, but without the need for additional cables and additional hardware units.
Related Resources
Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation
Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification...
TAGS: Architecture Design, Architecture Validation, TLM, Vista, Veloce2, TestBench XPress
Veloce System-Level Power Analysis and Verification
Power analysis and verification need to move to the system level, improving upon and extending the capabilities and scope of RTL and gate-level techniques. The performance, capacity, and flexibility of...
TAGS: Emulation, Veloce, Veloce2
Off-line Debug of Multi-Core SoCs with Veloce Emulation
On-demand Web Seminar 32:04Off-line Debug of Multi-Core SoCs with Veloce Emulation
Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design...
TAGS: Emulation, SoC Verification, Questa Codelink
