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Seamless

Ideal Platform for HW/SW Integration

Seamless enables users to debug hardware/software integration issues early in the design cycle by running embedded software on a simulation model of the embedded hardware. Seamless delivers full debug control and clear visibility of the interaction of hardware and software in your processor-based embedded design. Seamless provides an ideal platform for identifying critical HW/SW integration issues prior to the availability of an FPGA or silicon prototype.

Using the Seamless HW/SW integration techniques, embedded software and physical hardware arrive at system integration completely verified so only minor optimizations remain at system bring-up. By combining the full visibility of the hardware through the logic simulation and verification environment with a graphical, source-level debugger of the processor running as an instruction set simulator (ISS), Seamless provides you with the information and control necessary to quickly isolate and correct design errors.

Seamless gives you complete control of the interaction of the detailed hardware simulation and the processor instruction set simulator. The underlying Seamless technology enables you to accelerate the overall simulation and processor instruction performance. Seamless controls the processor ISS contained in the Processor Support Package, the patented Coherent Memory Server technology, and also reduces the overhead between the processor ISS and the logic simulator. The Processor Support Package wraps the vendor-supplied processor ISS model with a bus interface model (BIM) to provide a pin-level interface of the ISS to your hardware design.

The Coherent Memory Server controls and maintains optimized and non-optimized memory accesses by the ISS and the logic simulator. You have full control of the memory and timing optimizations so that the processor overhead for instruction and memory accesses are de-coupled from the logic simulation. After you have verified the non-optimized memory accesses, you can optimize those accesses to reduce the overall simulation time.

The Seamless HW/SW integration techniques complement and enhance Processor Driven Verification (PDV), OVM, and Assertion Based Verification (ABV) for a complete functional verification solution.

Details

Features

  • Best in class HW/SW Integration. Full visibility and control of hardware and software execution
    • Dynamic performance optimizations
    • Wide selection of processor cycle-accurate models created and validated by the CPU vendor
    • Charts key design performance characteristics
  • Easy to adopt. Only minimal hardware and no software changes required. Replace the processor in the design with a pin-for-pin compatible processor support package (PSP) based on a vendor-supplied processor model.
  • TLM inter-operability. The TLM interface of the processor models may be used to communicate with OVM testbenches and SystemC components in the system.

Benefits

  • Reduce Risk. Reduces risk of schedule slip at system integration
    • Eliminates hardware prototype iterations
  • Accelerate software and hardware debug. Remove software from the critical path in your project.
    • Detects and isolates hardware/software interface errors months ahead of hardware prototype.
  • Multi-core designs. Debug multi-core synchronization errors.
  • Maximize Design Throughput. Identifies hardware/software performance bottlenecks.

From the Blogs

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What Customers are saying...

“Besides the normal CPU bus access for program and data RAM, when DMA bus access was utilized, only Seamless was able to maintain the simulation speed. Other tools' performance degraded and could not handle basic simulation routines.”

Hiroshi Sugawara, Sony Semiconductor Manager

“Even given Alcatel's advanced system debugging methodologies, co-verification yielded a much greater observability and controllability of the system.”

Gjalt de Jong, Alcatel Antwerp Facility

“With Seamless, we can enable the software development to begin before any hardware is done, and that has been a major bottleneck in the past.”

Antti Suhonen, Nokia Hardware Engineer

 
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