Dot Hill Systems Increases Productivity and Reuse with Mentor AVM

Today’s highly complex, high throughput designs require the advanced verification functionality that only SystemVerilog’s objectoriented capabilities can provide—including constrained-random tests, transaction-level modeling, and assertions. Dot Hill determined that only Questa and the AVM offered the level of SystemVerilog support they needed. They were not disappointed in the results: a testbench with four to five times the functionality at one-third the size, built quickly and easily by a small team.

“The thing that really led us to Questa and the AVM was the fact that they allowed us to use the power of the SystemVerilog language a lot better than any competitive solutions would have.”

 Headquartered in Carlsbad, California, Dot Hill Systems Corporation has offices in China, Germany, Israel, Japan, the Netherlands, the United Kingdom, and the United States. For over 20 years, Dot Hill’s RAID technology has been the foundation for best-inclass storage solutions offering enterprise-class security, availability, and data protection.

With the level of high performance, high reliability, and high data throughput they needed in their latest RAID accelerator chip, the four members of the design and verification team at Dot Hill’s Longmont Technology Center could read the writing on the wall. Verilog could not deliver the capabilities their testbench needed to verify their next-generation multi threaded design. They relied on an FPGA prototype for final testing, yet they were aware of all the advantages of verification and debug at the register transfer level.

The RAID accelerator performs all the data movements and all the RAID 5 and RAID 6 calculations. There are many different, concurrently active interfaces. Fibre channels feed data into the chip from the external system, and on the back end there are 12 to 108 fast disk drives. Internally, a couple gigabytes of data per second are accelerated through the chip, which includes all of the I/O interfaces and a RAID accelerator. There are typically 20 different threads of traffic going through the chip at any given moment, all interacting with each other. Thus, the chip must be able to simultaneously handle the incoming data, generate the DMAs, and perform heavy duty RAID calculations in and out of the DRAM. Consequently, a lot of concurrent traffic has to be generated and checked.

Their existing testbench environment used directed and random tests written in Verilog, with some C code and a few perl scripts. While this methodology had worked well for previous designs, the next-generation device was more complex, and Dot Hill realized that they needed higher level capabilities to manage the complexity.

“The limitations of Verilog impelled us to switch over to System Verilog and the AVM,” recalls Don Allingham, Principal ASIC Design Engineer at Dot Hill Systems. “The size of our team also pushed us toward a constrained random testbench. With a small team, there was no way we could go the traditional route of writing lots of manual, directed tests.”

Keeping track of all the different threads of data requires higher level data structures than available in Verilog. For example, using Verilog designers must model memory with fixed array sizes, which can become problematic, especially with the large memories that Dot Hill had to model. Conversely, SystemVerilog packs the powerful capabilities that Dot Hill needed, including associative and dynamic arrays.

“With good object-oriented programming, as supported by SystemVerilog, we could instantiate objects that generate traffic for each stream then funnel it all into a single TLM FIFO,” Mr. Allingham continues. “This drastically cut down the maintenance and design efforts.”

 Going with the Best

The Dot Hill team had been following the development of the SystemVerilog standard for a while. So when it came time to address their Verilog testbench’s capability issues, they started looking at the various methodologies available. After evaluating the three leading solutions, they decided to go with the Mentor Graphics® AVM solution and Questa® advanced verification platform.

“We were rather surprised how quickly we were able to bring up a working testbench,” Mike Peters, Principal ASIC Design Engineer at Dot Hill Systems, observes. “The AVM training class Mentor offers was very critical to our success by helping us to hit the ground running. It took us about two weeks to architect our testbench, devise our policies, and learn the quirks of AVM. This was significantly less time than we expected.”

“There were a few major reasons we chose the AVM,” Mr. Allingham adds. “One, it was open source, which meant we weren’t going to be locked into a proprietary environment. Second, the AVM merged nicely within our existing environment because it was pure, standard SystemVerilog. There weren’t any artificial barriers between the test environment and the design and simulation portion. Every other verification methodology had some type of a barrier between them. They just didn’t fit nicely together. On top of that, the AVM is structured so much better; it’s much more maintainable. The TLM FIFO is probably what sold us more than anything else.”

With all the different threads of traffic starting and stopping throughout their test, keeping track of all the data and verifying it as the test was running was difficult in Verilog. The AVM TLM FIFOs allowed them to develop each portion of the traffic as independent threads using the same transactor models, with each thread generating its own traffic and putting it into the FIFO.

The AVM helped the Dot Hill team do things they couldn’t do before. Functionality that previously was tested on an FPGA prototype could now be verified at the RTL level. For example, the AVM enabled them to take advantage of SystemVerilog to create drivers that generate and verify RAID 6 traffic on the fly. Furthermore, they could add that to all the rest of the traffic, something they were not able to do before. It also enabled them to increase their coverage and verify at a higher level of abstraction, at the RTL, where it’s easier, faster, and cheaper to fix bugs.

“The AVM testbench has already helped us catch several problems that the old testbench was not capable of handling,” Mr. Peters reports. “There were things we couldn’t have tested in Verilog that became very easy to do with SystemVerilog and the AVM. Each individual thread became very simple to deal with. We could easily add as many threads of traffic as we wanted. Because everything was object-oriented, we dealt with one thread of traffic at a time, and a lot of the threads became almost trivial to write. Before, we had to write a lot of high-level code to manage different threads.”

A Leaner, Meaner Testbench

Dot Hill decided to use their current FPGA to test the new platform. The testbench they wrote around the AVM was a third the size of the Verilog testbench; yet it generated four to five times the functionality. The AVM allowed them to run several concurrent threads, each generating its own kind of traffic at the same time. This enabled them to write much more complex and difficult tests. The experimental code proved to be robust enough that they unequivocally dropped the old testbench in favor of the AVM testbench.

“Prior to the AVM, we had to debug RAID 6 on an FPGA prototype within the system using FPGA debugging tools,” says Mr. Allingham. “With the AVM, we were able to generate a significant amount of traffic and enough randomization that we were able to fully verify the design at the RTL level.”

“The AVM uncovered lots of hidden bugs because of SystemVerilog’s ability to do concurrent testing using constrained-random techniques,” Mr. Allingham explains. “It would have been almost impossible to do directed tests for all the threads of traffic and corner cases we had. Now, instead of relying on the prototype environment to catch problems, most are caught at the RTL level.”

“We definitely found bugs that we wouldn’t have found with the old Verilog environment,” Mr. Peters agrees. “We developed this new testbench, we started writing random tests against the same design, and we found bugs that would have been very difficult to diagnose because they’re deep down inside the serial links. These problems are very difficult and time consuming to diagnose. But in simulation, you can see down inside everything. This not only made it easier to detect bugs, but also made it easier to diagnose the problems.”

Lessons Learned Still Apply

Testbench reuse was another important consideration for the Dot Hill team. Facilitated by the AVM’s emphasis on reusable components, almost the entire testbench will be migrated into their next, much larger, higher performance design, which features faster interfaces and much higher levels of integration. They also plan to use more assertions and place a greater emphasis on coverage, both of which are supported by the AVM.

“We were able to use assertions here and there in our new testbench,” Mr. Allingham confirms. “And any future code that we develop will have assertions as well. The next generation design will involve many more assertions within the design and coverage aspects of the testbench. We use a lot of third party IP, so we’re learning how to use coverage on third party IP, and, similarly, we’re interested in the Questa Verification Library with the AHB and APB interfaces.”

By delivering a truly open source, pure SystemVerilog methodology, backed by outstanding support, the Mentor Graphics AVM was unmatched in the industry. With the AVM, smaller design and verification teams, as well as larger ones, can produce highly complex designs using smaller more powerful testbenches.

“The thing that really led us to Questa and the AVM was the fact that they allowed us to use the power of the SystemVerilog language a lot better than any competitive solutions would have,” Mr. Allingham concludes. “And we’ve always had good luck with Mentor’s support and application engineers. That’s always a critical factor for us.”

“The AVM testbench has already helped us catch several problems that the old testbench was not capable of handling. There were things we couldn’t have tested in Verilog that became very easy to do with SystemVerilog and the AVM.”