Questa and AVM Boost Verification Productivity and Quality at Hynix
Questa’s support of SystemVerilog delivers testbench automation, assertion-based verification, and the Advanced Verification Methodology to Hynix. By improving productivity, this winning combination helped Hynix tape-out two bug-free chips two months faster than expected within the project schedule.
“Questa enabled us to do three very important things on both of these designs. It shortened our development time by two months, got us quickly to zero functional bugs, and helped us achieve two successful tape-outs ahead of schedule.”
Learn More About Questa and SystemVerilog
product overview: The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF
Based in Seoul, South Korea, Hynix Semiconductor, Inc. is a titan among Flash memory and DRAM makers. Recently, its Flash Division was looking for a better way to design and verify their 8 GB and 16 GB NAND Flash chips. Not only were they faced with the challenge of producing these enormous Flash drives, but also they were venturing into the realms of 57 nm (for the 8 GB memory) and 48 nm (for the 16 GB) geometries.
Experience told them their current verification approach, relying on several hundreds of manually written, directed tests, would not allow them to thoroughly verify these very complex designs and meet their tight time-tomarket deadlines.
“We needed to reduce our turnaround time and improve verification performance,” reports YoungSoo Park, Senior Engineer, Hynix Flash team. “Our goals were, and are, to have zero functional bugs in our designs and shorten the overall Flash design cycle.”
The Flash design and CAE teams determined that the way to achieve these goals was to switch to an automated testbench methodology that replaced directed stimuli with constrained random test generation and added several advanced verification techniques to their design and verification flow. They also wanted to use the same verification environment for both block-level and system-level verification.
These techniques are most effectively and efficiently implemented using a standard design and verification language such as SystemVerilog. SystemVerilog facilitates the successful adoption of constrained-random test generation, assertion-based verification (ABV), and testbench automation (TBA).
Although, the Hynix Flash and CAE teams were using another simulator at the time, after evaluating the options, they chose Questa® from Mentor Graphics® for its built-in support of SystemVerilog, pioneering advances in ABV, and seamless compatibility with the Advanced Verification Methodology (AVM).
“We wanted to automate our testbench and insert assertions using SystemVerilog,” recalls WooSik Choi, Senior Engineer, Hynix CAE team. “Questa was the first to support SystemVerilog and deliver a SystemVerilog methodology.”
“From our experience using Calibre®, we knew we’d also get excellent engineering support from Mentor Graphics and their Korean distributor, ED&C,” adds Mr. Park.
After evaluating the Mentor Graphics advanced verification solution, Hynix decided to build their functional verification system for NAND flash memory using Questa and the AVM.
“With design complexity growing and process technology decreasing, it is critical to have a tool like Questa that can verify the full design faster than other tools,” observes Mr. Park. “We had been searching for the solution, and Mentor Graphics provided it along with aggressive engineering support in SystemVerilog and the AVM. They also helped us meet our time-to-market requirements by setting up the environment before we started a new project.”
SystemVerilog Furthers Advanced Technologies
Design complexity means that verification teams must be able to produce more tests with less redundancy to cover targeted features more quickly. The optimal verification solution helps engineering teams travel a path to higher verification productivity via the application of advanced verification technologies and methodologies.
Effective verification requires two critical elements, both of which are promoted by SystemVerilog. First, the verification environment must be set up to detect bugs as automatically as possible, which is where features like assertions, automated response checkers, and scoreboards come in handy. Second, it must be able to generate the proper stimulus to trigger bugs. Stimuli may be generated via either directed tests or constrained random techniques that exercise a wide range of scenarios with a relatively small amount of code.
TBA is achieved through the use of constrained-random simulation, in which each “test” actually describes a set of possible scenarios, while the simulator itself chooses a specific scenario for each invocation. SystemVerilog allows users to describe stimulus scenarios in terms of constraints, which limit the set of legal values for signals or transactions that drive the design. The simulator thus generates random values for stimuli, with the constraints ensuring that the generated scenarios are valid. A new scenario is run simply by re-running the simulator with a different random seed, causing different, but equally valid stimuli to be generated, thereby potentially checking untested features.
The use of randomization and constraints offers many substantial improvements in verification productivity. Once randomization is incorporated in the testbench, functional coverage is required to determine which of the possible scenarios actually occurred. SystemVerilog functional coverage tracks which functions of the design were exercised, so time is not wasted exercising the same ones.
“We used testbench automation to verify various test cases,” Mr. Park says. “Constrained random testing enabled us to run a full range of tests and improve the total coverage rate.”
SystemVerilog also allows assertions to be specified directly. An assertion is a statement of design intent that captures knowledge about how a design should operate. Embedded assertions improve observability, enabling problems to be identified immediately as they happen, where they happen. ABV enables project teams to perform functional verification on system-on-chip (SoC) designs more thoroughly and predictably than with HDL simulation alone, resulting in higher quality designs that meet aggressive time-tomarket windows and help project teams tape-out with confidence.
“Questa’s TBA and ABV capabilities, its leading support of SystemVerilog, and proactive engineering support were integral to reducing development time,” explains Mr. Choi. “The return on investing in the Questa solution was definitely positive.”
Applying an Automated Verification Flow
The Hynix team established a toplevel verification flow using Questa and the AVM to do behavioral modeling and RTL simulation of their design. SystemVerilog TBA and ABV within the AVM framework helped them successfully move from their manual, block-level approach to automated block and system level verification.
“Mentor Graphics and ED&C helped us set up the verification environment and provided engineering support, including SystemVerilog training, Questa training, script translation from our old simulator to Questa, and more,” says Mr. Park. “Once we were up and running, we found the Questa environment to be very powerful and user friendly.”
Whereas they would not have been able to meet the time-to-market and engineering requirement with their old methodology and tool, the Hynix team enjoyed good results on two completed projects, the 8 and 16 GB Flash memory chips.
“Questa enabled us to do three very important things on both of these designs,” reports Mr. Choi. “It shortened our development time by two months, got us quickly to zero functional bugs, and helped us achieve two successful tape-outs ahead of schedule.”
More Good Things Ahead
Pleased to complete their project successfully by adopting the Questa solution, Hynix is now using Questa on two new chips currently under development. As well, Hynix is planning to use the Questa verification solution for all Flash Division projects, including a 32 GB design currently in progress.
“The Mentor Graphics tools and methodologies have been adopted successfully in our verification flow and will be a major verification methodology at Hynix in the future,” says Mr. Park. “Because of our success we have requested aggressive development and support from Mentor Graphics on other technologies such as functional coverage, dynamic formal, and clock domain crossing verification.”
“The Mentor Graphics tools and methodologies have been adopted successfully in our verification flow and will be a major verification methodology at Hynix in the future.”
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WooSik Choi and YoungSoo Park
are Senior Engineers at Hynix.
“Questa’s TBA and ABV capabilities, its leading support of SystemVerilog, and proactive engineering support were integral to reducing development time. The return on investing in the Questa solution was definitely positive.”