IMEC Uses TBX and ARM IP Xpress Target Platform to Achieve Accelerated Verification of a Multi-Mode Multimedia Terminal
When IMEC needed to rapidly verify its multi-mode multimedia (M4) terminal of the future, it utilized the Mentor Graphics® TBX™ and ARM IP Xpress Target Platform™ (IPxTP) solutions with hardware-assisted verification. Using this combined technology from Mentor, IMEC verified the complete functionality of its Flexible Air Interface modem and multimode multi-format codec (3MF) platform. By directly mapping its SystemC transaction level models in TBX and quickly running exhaustive test sequences, IMEC saved months on testbench execution and creation. With TBX and ARM IPxTP, IMEC ensured that their software was ready and debugged before the chip returns from the foundry.
“With Mentor TBX and the ARM processor, IMEC’s engineers are able to have the software ready and debugged before the ASIC is back from the foundry.”
Maryse Wouters, IMEC
Creative Verification as Crucial as Creative Design
In the world of nanoelectronics and nanotechnology, producing highly complex products within a short time frame is crucial to business success. IMEC’s world-leading independent research center is focused on the next generation chips and systems and the enabling technologies for ambient intelligence. This requires creativity and execution not only from the design side, but from the verification team: It is critical to get the design right the first time.
IMEC started the M4 project in 2004, which is finalizing now. The M4 project is a fundamental component of a wireless platform that can access services and information at home, in the car, at work, even when walking in urban areas or desolate environments — services such as video conferencing, movie-watching, multi-platform gaming, all of which allow a seamless experience during roaming.
IMEC’s research is focusing on the mobile terminal aspect of this vision, tackling complexity, throughput, latency, cost, battery lifetime and time-to-market for successive product versions.
Rapid product development for a highly competitive market is a must. The verification time savings is a part to accelerate delivery to customers.
Accelerated Verification with TBX Needed for Full Testing Coverage
IMEC needed to verify its Flexible Air Interface (FLAI) and 3MF platforms prior to producing them in silicon. The company knew that simulation alone would be inadequate to obtain the testing coverage they required within project deadlines; they required the tremendous speed of an emulator to run long test sequences in an acceptable time frame.
In mid-2005, IMEC selected Mentor’s TBX and ARM IP solutions based on some of the products more compelling capabilities.
First, TBX can handle large designs greater than ten million gates with high performance. This capacity was more than adequate to verify the five million gate FLAI platform, where emulation speeds were two orders of magnitude faster than software execution speeds.
Second, TBX contained its own RTL compiler, so IMEC was not required to purchase additional FPGA synthesis and partitioning tools for a complete solution.
Third, the replay capability offered substantial time savings to the verification team. If after running emulation, the engineers found they needed extra signals but had not already made them observable, they could use TBX’s replay function to calculate the value of additional signals, enabling them to obtain information on other nodes. The replay step only took fifteen minutes to execute, eliminating the need for an overnight run previously required. Additionally, TBX preserved names such as internal buses throughout the flow, even after RTL compilation.
IMEC also valued Mentor’s automated memory inference. IMEC’s engineers could specify the name and the size of the memory in one file, and the memory would be allocated on the emulator. This easy step allowed a fast start to verify the functionality of the FLAI and 3MF platforms.
Firmware Testing Before Chip Completion
IMEC can map the firmware for different wireless standards that would run on the FLAI platform, such as WLAN, 802.16e and 4th generation 3GPP-LTE, on the emulator.
“With Mentor’s TBX and ARM IPxTP solution, IMEC’s engineers are able to have the software ready and debugged before the ASIC is back from the foundry,” said Maryse Wouters, Activity Leader Integration Team, Nomadic Embedded Systems Division at IMEC. Wouters and her colleagues were able to dramatically reduce the time to validate that IMEC’s low power digital modem correctly handled multiple wireless standards going from in-house WLAN to cellular links.
Mentor’s ARM IPxTP Allows Synchronized Breakpoints
When used in conjunction with TBX, Mentor’s ARM IPxTP solution gave IMEC flexible communication between its ARM core and the TBX-based acceleration, providing verification and debug at emulation speeds that are several orders of magnitude faster than software execution speeds.
IMEC 3MF MP-SoC consists of ARM 926,
Network-on-Chip, and multiple Adres processors.
For IMEC’s FLAI application, the ARM boot code was loaded via the host interface. Once this instruction set was loaded, ARM commenced executing the instructions.
IMEC found that having the ability to define triggers in a finite state machine is very useful for debugging. The triggers were based on ARM addresses, interrupts, and stimuli counts. By using Mentor’s ARM IPxTP solution with TBX, IMEC synchronized the ARM debugging with hardware debugging. By aligning the triggers at breakpoints on the ARM when designing their state machine, IMEC engineers could simultaneously debug the software running on the ARM and the remainder of the 3MF and FLAI platform.
When each trigger was reached, IMEC engineers could go step by step through the instructions of the ARM. Thus they could debug the software running on the ARM while simultaneously observing the hardware. This gave the engineering team full observability before and after the trigger point as they searched for errors with their viewer.
100 Percent Observability
One of IMEC’s key verification requirements was full observability inside the design via a visual inspection of the internal nodes and the interconnections in the design. Hardwareassisted verification with TBX delivered this 100 percent observability — when IMEC’s verification engineers identified unexpected behavior, they can look at all of the nodes in the design and identify the origin of the problem.
Transactors Bring Communication Speed-up
IMEC used TBX for transaction level modeling (TLM) of a data streaming interface between the emulator and the PC host for their FLAI and 3MF platform.
On the 3MF platform running on the emulator, the encoding and decoding of the video stream is done. By using transactors with TBX, the detailed bus protocol with low-level bi-directional communication and acknowledgements with the data transactors is hidden. Mentor supported all the languages (VHDL, SystemVerilog, Verilog, and SystemC) needed for IMEC’s team to create the transactor model so they could load the data stream into the emulator and read it — with the transactor speeding up the communication link between the PC and the emulator.
From SystemC to RTL: One Environment, One Testbench
IMEC created a virtual model for the complete design in SystemC. In this case, the company made a transactionlevel model of the FLAI platform, so that early software development could be done.
Heterogeneous MPSoC for SDR baseband: Optimized
Flexibility vs. Energy.
IMEC used the same simulation environment for both their high level transaction level models and for emulation. This environment was composed of the PC, the emulator hardware, and the emulator software. IMEC ran a transaction level model on the PC and then used the ARM processor on the emulator.
The TLM model was coupled to the ARM IPxTP solution, which was connected to the emulator. Whenever a block in the TLM was refined and implemented in RTL, that block was mapped on the emulator hardware. By linking SystemC code to the emulator, IMEC was able to model the design, simulate it, map it to the RTL specification of the ASIC, and verify it. A major advantage of this approach was that IMEC could use the testbench at the TLM level and apply the same testbench with hardware-assisted verification. Another benefit was that when they moved the SystemC blocks to the emulator level, IMEC could verify that the implementation of the TLM block at the RTL level was functionally correct. In this way, the complete functionality of the ASIC was covered to avoid the risk of failure once the silicon is produced.
Success on Multiple Fronts
With the combination of Mentor’s TBX and ARM IP solutions, IMEC met its demanding verification needs for high-performance verification acceleration, 100 percent observability, and full testing coverage.
Mentor’s accurate, vendor-qualified IP models of the ARM processors allowed IMEC to reduce its risk and increase design confidence in the process.
IMEC was able to take advantage of Mentor’s plug-and-play, ease-of-use capabilities, such as debug connections to industry-standard software debuggers, to facilitate high-speed hardware-software co-verification.
Finally, the fast execution speeds of the ARM processor with emulation, which provides two to three orders of magnitude faster than software simulation — offers substantial improvements to the verification team’s productivity.
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M4 terminal SDR front-end.