Imagining New Realities at IME with the Support of Questa and the OVM
When designing the aggressive, real-time section of a unique system for visualizing the future and creating new realities in the present, the IME team found that the complexity of their FPGA algorithms required more advanced verification tools and a methodology to make them more productive. An excellent history with Mentor Graphics® and the promise of full SystemVerilog support inspired them to adopt Questa® and the Open Verification Methodology (OVM), with excellent results. Two particularly tricky problems were resolved that would have prevented the realization of this visionary reality.
“OVM gives you a real head start with all the classes provided. The classes are beautifully built one upon the other and there is a great consistency among them. The OVM actually simplifies complex verification compared to traditional verification.”
Laszlo Arato, Research Associate, Project Leader, IME
As part of an interdisciplinary research project, the Institute of Microelectronics (IME) at the University of Applied Sciences Northwestern Switzerland, developed the software and microelectronics for an FPGA-powered, physically small board that overlays selected sections of a video image taken of a surrounding landscape with a simulated image generated by a computer carried in a backpack. The result is shown in real time on a head mount display, which also carries the camera, attitude sensors (to determine the tilting of the persons head), and a GPS receiver. This combination of virtual and real-world images is known as augmented reality. IME and their partners are the only players to take this visionary technology out of the lab and into urban areas.
The goal of the interdisciplinary CTI project, “Lifeclipper 2” (www.lifeclipper.net), was to research how augmented reality can be used to visualize, for example, what an existing college campus would look like after the addition of one or several buildings. The challenge is to make the fusion of these real and the virtual images as seamless as possible, in spite of significant inaccuracies in the attitude sensors and viewing-direction compass and without the use of preplaced tags or markers.
The IME design contains one large FPGA, external memory chips, and the digital cameras. It is a single unit that receives images from the computer through one digital video interface connector and provides information on which areas to show and at what intensity through a second one. Thus, the IME board generates the augmented image directly on the head mount display, avoiding lengthy cables and delay issues.
During the development board stage, IME used the OVM testbench as implemented in Questa to find two critical bugs in the logic. One was a pipeline bug that prevented the image control signals from being delayed equally. The other was a saturation bug, where the color space translation was failing in certain corner cases due to a rounding problem.
Real time is one of the biggest challenges in augmented reality. As the viewer moves his or her head, the virtually generated image and the actual scenery must match exactly and keep on matching; otherwise, the illusion is broken. This requires a high-speed correlation between the two images to determine the offset between them and make the necessary corrections to sync them.
When an image needs to be rotated, the easiest way to make this adjustment is to first place the entire camera image sequentially into an input buffer, copy it pixel by pixel to an output buffer while applying the coordinate translation, and then read out the output buffer in a sequential way as the image is transferred to the display. This would, of course, require double-buffering on both the input and output sides. However, this can not be done in real time, so a single buffer is used. Performing all of these calculations in real time on streaming data, without the two intermediate buffers, requires very complex algorithms. In addition, for every pixel, three or four pixels must be read in order to interpolate the exact value, because the rotated image, pixel by pixel, will not match the original one.
The bit width of the single buffer presented even more complications. Because the buffer was only 16 bits wide, the 30-bit RGB signal had to be converted into the 16-bit YUYV color space. This enabled them to reduce the bits per color channel because the human eye is less sensitive to color (UV) than brightness (Y). Thus, IME was able to share the 16-bit chromaticity information equally across two adjacent pixels, while retaining 8 bits of luminosity per pixel, without a loss of quality. The result is the 16-bit per pixel YUYV color scheme.
Even though the transformation used to spread the chromaticity across the adjacent pixels was clearly defined as a couple of floating-point multiplications, the actual implementation was far from trivial. For example, the transformation formula used real numbers, with a lot of significant numbers after the decimal point, which had to be rounded before they could be converted into synthesizable logic. Depending on the actual rounding implementation used, some of the logic did not come out as intended, especially when it came to the representation of the different numbers in the corner cases.
Fortunately, by employing directed, pseudo-random test pattern generation, Questa and the OVM helped IME uncover these complicated rounding errors in the algorithm.
Before adopting Questa and the OVM, IME FPGA designers had used the common FPGA verification technique in which the design is implemented in a circuit and simulated. But they did not have that luxury with the more complex functionality of this design. Mr. Arato wanted a verification environment that fully supported multiple languages. Questa and the OVM were unparalleled in providing that solution.
“We decided we needed to focus more on verification.” recalls Laszlo Arato, a research associate and project leader at IME. “I have used a couple of products before, such as the verification language e. They were never really up to date to the extent that we are with SystemVerilog and the OVM.”
IME designs in VHDL because of its strong typecasting and strict rules that force designers to write structurally clean code. On the verification side, the same rules that make the physical design very safe in VHDL block the flexibility needed for an efficient testbench design. However, the verification side and the design side must match and must be simulated within the same environment. This has remained a persistent challenge, until Questa. Questa gave them access to the flexibility they needed in the SystemVerilog verification language, while allowing them to design using the more strict VHDL language.
“We use VHDL for design and SystemVerilog for verification,” Mr. Arato explains. “Questa has a very nice way to integrate the two. The Questa interface has become extremely simple and straightforward. It was a great help to use the SystemVerilog objectoriented environment on one side and VHDL on the other side. SystemVerilog gives the flexibility to not worry about the real number space, rounding, and delays, and it is free of the constraints that are dictated in the physical design. VHDL allows me to keep things structurally clean for something that will be mapped down to gates and registers.”
OVM as an implementation of SystemVerilog provided a solid framework and basic constructs that the IME engineers were able to use to understand the technology behind the methodology and the object-oriented world.
“OVM gives you a real head start with all the classes provided,” Mr. Arato observes. “The classes are beautifully built one upon the other and there is a great consistency among them. The OVM actually simplifies complex verification compared to traditional verification. The construction of the test cases is faster than coding a similar test environment in VHDL, and we were able to use many OVM objects directly out-of-the-box, while only a few specific drivers needed to be coded by hand.”
By allowing IME to use a test file to individualize each stimulus generator in whatever way they chose, the OVM enabled IME to drive both directed and random tests on a single, maintained testbench. This gave them the flexibility to replace parts of the testbench on the fly, while preserving the rigidity of driving many directed tests on a single maintained testbench, which helps reduce the amount of work for the designers.
“The testbench itself is actually very simple,” Mr. Arato explains. “The testbench instantiates the DUT and the interfaces to it, leaving everything else to the object-oriented environment, which is tied-in over the simulation call with a test name. This allows me to match the DUT and test environment using signal names that otherwise have very few common ties.”
IME used some of the powerful features included in the OVM to help them with the rounding issue. For example, the team wanted to compare the output of two different streams of the Y, U, and V spectral data, limited to only the seven most important digits, ignoring small rounding differences. Because the comparator class, as part of the OVM, uses the compare function of the transactor, they were able to simply plug-and-play it into their test environment. The actual compare function itself is defined as part of the transaction class enabling IME to realize the configurable compare function not as part of a custom comparator, but by implementing it as the comp method in the transactor class.
They then used the unmodified ovm_in_order_class_comparator to do the actual work, housekeeping, and necessary reporting.
“This is an example of the beauty and the flexibility of the design of OVM,” observes Mr. Arato. “For me this was one of the big winning points that convinced me that OVM is the way to go. The in_order class comparator is a beautiful design entity by itself, with a lot of reporting and verification functions in itself.”
It Wasn’t Rose Colored Glasses
IME was initially steered toward Questa because of its success using other Mentor Graphics tools and the personalized support they got from Mentor Graphics Switzerland. When it came to adopting SystemVerilog and the OVM, Mentor support came through again—shortening the learning curve and responding quickly to any questions.
“You’re much better served using OVM, but initially you have to ramp up your knowledge of it,” Mr. Arato points out. “After the Mentor training division gave us a very thorough SystemVerilog course, Mentor Switzerland gave us an introduction course on OVM. We then went from AVM 3.0 to AVM 3.1 to OVM. We had very good support through Switzerland on what was new and what changed. Throughout that time, they were very responsive. If a problem was too tricky for them, then somebody from Mentor in Munich would respond to my emails within 24 hours or so.”
Mentor Graphics support, tools, and methodologies continue to help IME pursue unique and exciting advancements in research, higher education, and commercial products.
“Thanks to the development of an OVM testbench using Questa, we were not only able to positively verify correct functionality, but also find the last two bugs in the logic,” concludes Mr. Arato. “The Mentor support team has always been a phone call or email away, and their response time is very, very good. They’re great people, and they’re just great to work with.”
To learn more about IME, go to http://www.en.fhnw.ch/ime
“We use VHDL for design and SystemVerilog for verification. Questa has a very nice way to integrate the two. The Questa interface has become extremely simple and straightforward.”
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Laszlo Arato is a verification
specialist and an instructor
of virtual design and object
oriented programming at IME.
“The Mentor support team has always been a phone call or email away, and their response time is very, very good. They’re great people, and they’re just great to work with.”