Icron Forges into ASIC Territory with Questa Full SystemVerilog Support and SpectaReg Automated Register Generation
When you’re expanding into a new country, you need to become fluent in the language. Mentor Graphics and PDTi helped Icron pick up SystemVerilog and apply it to the verification of its first ASIC design. Questa supported all of the SystemVerilog features they needed and PDTi generated error-free SystemVerilog modules of the register specification.
“We set out to find a simulator that would allow us to use all the major features of SystemVerilog. We chose Questa because it had the best SystemVerilog support at the time.”
Aaron Hall, Design Architect, Team Leader, Icron
Founded in 1998 and based in Vancouver, Canada, Icron® is a leading designer, manufacturer, and marketer of innovative USB extension and bridging solutions. Icron has pioneered extended range solutions that solve the distance limitation of USB by increasing its maximum range from 5 meters (16 feet) to over 40 kilometers (24.8 miles). Its ExtremeUSB® technology is the only extension technology that has met the rigorous standards required by the USB Implementer’s Forum for product compliance testing.
Icron’s technologies are used worldwide in a diverse set of applications, such as supercomputer control and satellite testing and in an equally varied range of industries, including aerospace, automobile manufacturing, industrial automation, keyboard/video/mouse extension, medical imaging, movie production, and consumer PC to TV applications that enable users to interact with their PC content and applications on their TV.
Icron continues to develop creative solutions to problems that would otherwise limit the deployment of USB technology. Their ground-breaking ExtremeUSB® has proven to be just such a solution, extending remote USB connectivity across any media.
Recently, Icron decided it was time to move these designs from the FPGA into the ASIC realm—a first for the company—so that they could put this hot technology on a single chip to reduce the cost of deploying the technology. For a small-cap company that’s been FPGA focused, this is a significant undertaking from both a staffing and tool perspective.
FPGA developers typically have the relative luxury of testing a prototype then going back and fixing any errors. However, respins are too expensive in an ASIC flow to allow this approach. The upfront design process has to be much more rigorous and verification tools and methodologies become much more important. Design errors must be kept to a minimum and the design must be thoroughly verified before silicon.
This is why Icron turned to PDTi SpectaReg™ to reduce design errors and Mentor Graphics® Questa® to make sure the design was right the first time.
Reducing Risk in a New World
The new ASIC design integrates Icron’s patented ExtremeUSB® technology on a single chip, enabling true plug-and-play USB 2.0 and significantly reducing costs. The new ASIC is a true System-on-Chip (SoC). It contains mixed-signal USB PHY IP operating at 480 MHz, a 32-bit embedded microprocessor, complex custom logic, and support for a huge variety of link media interfaces.
In the full USB extension system, the ExtremeUSB SoC is a paired chip set. A local extender chip (LEX) is connected to a PC, while a remote extender (REX) chip is connected to remote input/output devices, such as keyboards, mice, webcams, and Flash drives. The REX can be in the same room, across the street, on the other side of an industrial or university campus, or across an entire city. Between those two chips is the transport media, which can be wireless, CAT 5 Ethernet, fiber optics, power line, and coax).
To assist them with this complexity and the move to ASIC design, the Icron ASIC Design Group, led by design architect, Aaron Hall, who was also involved in setting up the verification environment, began an evaluation of what they needed to successfully verify their design. Creating the verification environment was a big task as the USB validation environment had to model the behavior of hundreds of different USB devices as well as different USB host controllers driven by multiple operating systems, such as Windows XP, Vista, and 2000, MAC OSX, and Linux.
Among the primary considerations was the language they would use. They considered a pure Verilog approach but wanted the benefits of an objectoriented verification environment. Mr. Hall had used C++ and PLI/VPI, but the learning curve to get a new team up and running with those languages was too steep. It came down to either SystemC or SystemVerilog.
“SystemVerilog was the natural choice,” Mr. Hall observes. “We went for SystemVerilog mostly for the ease of implementation, as all of our designers knew Verilog so learning SystemVerilog would be a natural progression. The object-oriented (OO) nature of SystemVerilog really helped us tackle the complexities of creating a USB verification environment. OO allows you to take a problem and easily break it down into objects that can be more easily worked on in parallel.
Scouting the New Terrain
However, a year-and-a-half ago when the evaluation took place, there was not an overwhelming swing toward SystemVerilog, as there is today. When a company is ahead of the curve on adopting a new language it is difficult to find EDA tools that support it. Fortunately, they found a tool that was also ahead of the curve. Because Questa supported all the SystemVerilog features they wanted, Icron was able to fully implement standard SystemVerilog constructs.
“We set out to find a simulator that would allow us to use all the major features of SystemVerilog,” Mr. Hall recalls. “We chose Questa because it had the best SystemVerilog support at the time. Unlike the other vendors, there were no major unsupported features, which is not typical with new languages, especially a complex language such as System Verilog. This allowed us to start using all the language constructs right away without continually checking to see which were actually supported. Questa’s support for System Verilog was always ahead of the curve, which was outstanding.”
Questa’s SystemVerilog support also enabled Icron to run constrainedrandom variables in their verification environment. SystemVerilog allows stimulus scenarios to be described in terms of constraints, which limit the set of legal values for signals or transactions that drive the design. Questa generates random values for stimuli, with the constraints ensuring that the generated scenarios are valid. A new scenario is run simply by re-running Questa with a different random seed, causing different, but equally valid stimuli to be generated; thus ensuring that it is checking a new feature.
“Constrained-random simulation caught issues where we didn’t expect there to be any,” Mr. Hall reports. “Many overnight constrained-random traffic simulations resulted in us hitting unexpected corner cases.”
When employing constrained-random simulation it is important to make sure that the same scenarios are not repeated, which would waste simulation cycles, and that the design has been thoroughly exercised, which determines verification closure. Functional coverage shows which scenarios were exercised, so time is not wasted repeating the same ones. A full suite of coverage metrics (including functional, line, and code coverage) compiled across all simulation runs and aggregated in Questa’s Unified Coverage Database (UCDB) pinpoints when the design has been thoroughly, but not overly, verified.
“The Questa coverage features and the UCDB worked very well,” Mr. Hall recalls. “A web page shows all the coverage information we need to gauge, shows how broad our test cases are, and ensures we touched all corners of the design. We were even able to aggregate different testbenches and import smaller, block-level tests into coverage.”
Nothing Lost in Translation
The Icron team wanted to migrate all the registers from a third-party FPGA embedded processor, used on the previous design, into their ASIC’s custom processor. PDTi had just the tool for this application, SpectaReg.
“Many companies try to roll their own versions, and I’d even done that at a previous company,” Mr. Hall observes. “These are typically cruder solutions and don’t work as well, and I didn’t want to invest in the amount of work required to do that. I was very pleased to find there was a register automation tool that was mature and worked. SpectaReg was a good fit right from the start.”
From the user-defined register specification, SpectaReg auto-generates the SystemVerilog and RTL for the registers, C macros to access the register blocks, software models for verifying them, and formatted documentation. SpectaReg also inserts coverage points for the bit space of the registers.
In the standard approach to register specification, there is a great deal of manual effort and chances for misinterpretation. The specification is written and passed on to the different people and groups in the flow who all create different outputs based on it: for example, the designer who creates the registers for the ASIC; the software engineer who writes the driver that manipulates the registers; and the verification engineer who implements the software driver.
“SpectaReg eliminates all the tedious work,” Mr. Hall observes. “And it eliminates any errors that could be injected when transcribing the spec.”
Just as importantly, SpectaReg eliminates errors in translation whenever there are changes to the registers; for example, where they exist in the memory map or their function. SpectaReg ensures these changes are percolated down and implemented to all the different groups and individuals.
“Another benefit of SpectaReg is its ability to enforce change management,” Mr. Hall adds. “SpectaReg allows designers to change bit locations and move memory addresses with no impact to software or verification. This is the true value of SpectaReg, and it is very apparent when debugging embedded software or a SystemVerilog simulation. You never question if the driver is reading or writing the correct bits because it’s always correct. This has saved us many long evenings in the lab troubleshooting.”
This represents a significant time savings and greatly reduces the risk of introducing new errors. For example, one of Icron’s larger register modules underwent 73 register revisions. Without SpectaReg, that would have required the architect to personally check with each design and verification group to make sure that all those changes got percolated through on 73 different occasions, with each of those revisions threatening the introduction of bugs and misinterpretations of the specification.
New Frontiers Lie Ahead
Questa’s SystemVerilog support, advanced features, intuitive GUI, and excellent technical support have won over an initially skeptical Mr. Hall.
“Once we got Questa installed and started using it, it seemed like a different tool from the Mentor simulator I used a few years ago,” he says. “It was a very positive experience. The user interface was really easy to use, and it supported all the features of SystemVerilog that the team wanted to use. The Mentor support team was very knowledgeable and helpful the few times we needed support. It definitely improved my view of Mentor’s simulation tools.”
Likewise, SpectaReg has become a constant in Icron’s tool flow.
“SpectaReg has definitely helped us cut down on the number of bugs that we introduced when hand-translating a register spec to RTL, to software, and to verification code,” Mr. Hall recalls. “Its flawless translation of the register specification has made it indispensable. It’s something that we can depend on. PDTi is very responsive to our suggestions for tool improvements and also very responsive to any problems with the tool; they fix them quickly. The SpectaReg output is very readable—not always the case with auto-generated code—and templates allow you to customize the look of the generated code.”
Both of these tools are now adopted into Icron’s design and verification flow, and they plan to keep on using them to succeed in the land of ASIC.
Visit Icron at www.icron.com to learn more about their products.
“The Questa coverage features and the UCDB worked very well...The user interface was really easy to use, and it supported all the features of SystemVerilog that the team wanted to use.”
“SpectaReg has definitely helped us cut down on the number of bugs that we introduced when handtranslating a register spec...Its flawless translation of the register specification has made it indispensable.”
Design architect, Aaron Hall,
led the Icron ASIC Design Group
and was involved in setting up the
new verification environment.
“Another benefit of SpectaReg is its ability to enforce change management...You never question if the driver is reading or writing the correct bits because it’s always correct. This has saved us many long evenings in the lab troubleshooting.”