Success Stories
Verification Success
Next Generation in Verification
Hear from Tom Fitzpatrick, a Verification Technologist with Mentor Graphics.
Next Generation in VerificationTestimonial
Xsigo Systems
Questa and the OVM facilitate Xsigo’s move to a constrained-random verification methodology, efficiently delivering higher verification productivity and design quality and helping them to attain their goal of a robust, cutting-edge FPGA on time. More
ON Semiconductor
Mentor’s Questa® mix-language simulator and Open Verification Methodology (OVM) library accelerated ON Semiconductor’s adoption and successful application of automated constraint-driven stimuli generation and coverage data collection. More
AMCC
Applied Micro (AMCC): The data processing, transport, and storage giant chose 0-In CDC for its usability and immediately achieved excellent results. More
Mitsubishi
Veloce hardware-assisted verification technology fits in perfectly with the electronics giant’s efficient verification methodology. More
SEAKR
SEAKR The aerospace data storage company quickly set up advanced testbenches with Questa that found more bugs and in record time. More
Sun Microsystems: Multi-Clock Design
The innovative multi-clock architecture of the Sun® UltraSPARC™ T1 processor required a unique clock-domain crossing verification solution that only 0-In® could deliver. More
Sun Microsystems: Three-Million Gate Design
Paul Gingras, design verification manager at Sun Microsystems, was responsible for the verification of a large ASIC developed for a high-end server with several very large, very complex components. More
Tensilica
Tensilica's Xtensa™ processor is a configurable and extensible 32-bit microprocessor architecture and support environment that enables embedded system designers to build better, more highly integrated products in significantly less time. More
National Semiconductor
Gordon Mortensen at National Semiconductor turned to Mentor's 0-In Assertion-Based Verification to find "bugs early enough in the design that we are not impacting our schedule with bug corrections." More
Olivetti
Olivetti standardized on Mentor Graphics® HDL Designer Series™ to manage the entire design process. HDL Designer Series provides a unique solution for integrating various design tools together to create a standardized flow for all designers. More
Advanced Micro Devices
AMD verifies complex orocessor and wireless chipsets with the Mentor Graphics O-In Verification Business Unit ABV Suite. More
Dot Hill Systems
Dot Hill determined that only Questa and the AVM offered the level of SystemVerilog support they needed. They were not disappointed in the results. More
Evatronix IP
Mentor Graphics® 0-In® Formal Verification improves the quality of Evatronix IP through exhaustive coverage, proven industry protocols and checkers, as well as support of assertion-based verification. More
Hynix
Questa’s support of SystemVerilog delivers testbench automation, assertion-based verification, and the Advanced Verification Methodology to Hynix. More
Hyperstone: ModelSim with SystemVerilog DPI
Hyperstone accelerates its RTL-simulation by raising the level of abstraction from netlists to C models. This was made possible through the SystemVerilog DPI in ModelSim®. More
Hyperstone: SystemVerilog DPI
The Questa SystemVerilog DPI enabled development of an enhanced Hyperstone mixed-language testbench, including the integration of an ISS C model and a software debug environment. More
Icron
Icron forges into ASIC territory with Questa Full SystemVerilog support and SpectaReg automated register generation. More
Institute of Microelectronics
The IME team found that the complexity of their FPGA algorithms required more advanced verification tools and a methodology to make them more productive. More
“ModelSim makes the task of integrating C code in the RTL simulation a very straightforward, three step process. Many helpful features make it easy to learn.”
Arthur Freitas, Development Engineer, Hyperstone AG. Read more