Mentor’s Questa® mix-language simulator and Open Verification Methodology (OVM) library accelerated ON Semiconductor’s adoption and successful application of automated constraint-driven stimuli generation and coverage data collection.
“Questa and OVM provided us with the SystemVerilog CDV solution that fit all of our needs and helped us reduce the effort needed to develop the verification environment and stimuli.”
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The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF
Best-in-class design calls for leading verification methodology
The ON Semiconductor Automotive Power Group division in Brno, Czech Republic, produces high-performance, power-efficient SoCs that feature best-in-class EMC and ESD automotive requirements, top-in-class IP, and mixed-signal sensor interface signals.
Recently, ON Semiconductor successfully designed a new mixed-signal, multi-function SoC within a tight six-month timeframe. Questa and the OVM provided automated, constraint-driven generation of stimuli and coverage data collection, enabling ON Semiconductor to achieve 100 percent functional coverage and build a more sophisticated testbench in half the time it took to build their previous, directed test environments.
Building a better verification environment
The ON Semiconductor team saw CDV as the most effective way to fulfill their goals. They had tried doing this with automated checkers, but writing them in pure VHDL was extremely complex and took too much time. System Verilog Assertions (SVA) and cover groups allowed them to get the information they needed concerning functional coverage.
“Our chief motivation was a reduction of effort and time,” recalls Digital Group Leader Marek Hustava. “We also thought we could increase design quality if we were able to report directly from the tool when we reached 100 percent functional coverage.”
Creating confidence and time
The ON Semiconductor team found the OVM testbench to be easy to reuse, reliable, and efficient, saving them effort and cost.
“With OVM we were able to prepare the testbench two times faster than the traditional way,” Mr. Pierscinski estimated. “Questa and OVM provided us with the SystemVerilog CDV solution, which fit all of our needs, and helped us reduce the effort needed to develop the verification environment and stimuli.”
According to Petr Tichy, Verification Specialist at ON Semiconductor, “The OVM let us make a visible step towards efficient functional verification. It proved its strength and flexibility for testing our transceiver chips. The TLM-based, constraint-driven stimuli mechanism enabled us to test virtually an infinite number of input combinations in a reasonable time.”
Because 100 percent functional coverage was reached in digital verification, the verification team was able to confidently identify all issues prior to mix-signal simulation. Therefore, it was no surprise that during mix-signal simulation no digital issues were detected. This significantly reduced the overall design and verification time. Using OVM methodology, ON Semiconductor has been able to produce a high quality IC in a significantly shorter timeframe compared to a traditional digital design and verification methodology.
“Using the OVM, we were able to produce a high-quality IC in a visibly shorter time in comparison to a traditional digital design and verification methodology.”
ON Semiconductor™ is a leader in power efficient semiconductor solutions for a wide range of markets. The company’s broad portfolio of products includes power, analog, DSP, mixed-signal, advance logic, clock management, and standard component devices.
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