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STMicroelectronics: Simulation + Emulation = Verification Success

In 2012, STMicroelectronics began a pilot project to build what it called the Eagle Reference Design, or ERD. The goal was to see if it would be possible to stitch together three ARM products — a Cortex-A15, Cortex-7 and DMC 400 — into one highly flexible platform, one that customers might eventually be able to tweak based on nothing more than an XML description of the system.

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Co-Emulation, Questa, Questa® Advanced Simulator, TestBench XPress, Veloce, Veloce2, verification IP

It's not enough to just say ‘go to the emulator,’ because too often this means making radical changes to the verification environment, a problem I’ve experienced on other projects. What we wanted to do was to take the same verification environment that we have in simulation and use it, with only small modifications, on the emulator.”

Lanfranco Salinari, ST SoC verification engineer

The Problem: Based in Italy and India, engineers at STMicroelectronics sought to understand and benchmark a combination of ARM components at the heart of a new SoC reference design. To speed this benchmarking along, they wanted a verification environment that would link software-based simulation and hardware-based emulation in a common flow.

The Solution: The first step: building a testbench for the Questa Advanced Simulator, in the process relying heavily on Mentor Graphics verification IP (VIP). Next, the team connected this testbench to a Veloce emulation system via TestBench XPress (TBX) co-modeling software. Running verification required separating all blocks of design code into two domains — synthesizable code, including all RTL, for running on the emulator; and all other modules that run on the HDL portion of the environment on the simulator (which is connected to the emulator). Throughout the project, the team worked closely with Mentor Graphics to fine-tune the new co-emulation verification environment, which requires that all SoC components be mapped exactly the same way in simulation and emulation.

The Results: Because the reference design was not bound to any particular project, the main goal was not to arrive at the complete verification of the design but rather to do performance analysis and establish verification methodologies and techniques that would work in the future. In this they succeeded, agreeing that when they eventually try this sort of combined approach on a real project, they will be able to port the verification environment to the emulator more or less seamlessly.

Our customers want assurance that we are using state of the art verification.”

Alberto Allara, ST verification engineering manager

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