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Verifying Tensilica’s Configurable Processor Core

Tensilica provides application-specific microprocessor solutions for single chip systems. The Xtensa™ processor is a configurable and extensible 32-bit microprocessor architecture and support environment that enables embedded system designers to build better, more highly integrated products in significantly less time. The environment includes an infrastructure to support the engineers most knowledgeable about the specific application requirements, so they can reliably and quickly add specialized functions or instructions to the processor and have them recognized as “native” by the entire software development tool chain.

Questa finds tough bugs that require a lot of unusual conditions to happen all at once.”

Kaushik Sheth, Chief Engineer, Tensilica

Major product features:

  • Nearly 300 Questa checkers were placed in the highly-configurable Xtensa core
  • More than 80 Questa checkers captured rules for the processor interface
  • Questa tools ensured thorough verification of the core prior to delivery
  • Configurable Questa checkers for the Xtensa processor interface enable rapid integration and reduced support costs

Adaptive Checkers Instrument Configurable Logic

Tensilica provides application-specific microprocessor solutions for single chip systems. The Xtensa™ processor is a configurable and extensible 32-bit microprocessor architecture and support environment that enables embedded system designers to build better, more highly integrated products in significantly less time. The environment includes an infrastructure to support the engineers most knowledgeable about the specific application requirements, so they can reliably and quickly add specialized functions or instructions to the processor and have them recognized as “native” by the entire software development tool chain.

Tensilica provides processors to its customers as synthesizable RTL cores. Since these IP cores are customer-configurable, there are thousands of potential configurations. Gate count is configuration dependent and can range from 25,000 to 150,000 gates or more. Gate count increases when the customer adds new instructions or optional features.

Tensilica’s primary verification challenges are 1) to extensively verify the configurable processor to ensure that each customer configuration is bug free and 2) to enable the customer to rapidly integrate the core while limiting support costs. Meeting these challenges requires verification tools and a methodology that accelerate the verification cycle for both the core creator and the core integrator.

Enhanced Verification Environment

To verify different configurations of the Xtensa architecture efficiently, Tensilica uses a configurable test environment that generates customized diagnostics for the processor instance under test. This environment integrates with pseudo-random stimulus generation and supports co-verification with an instruction-set simulator (ISS).

Stimulus is applied at the instruction level and the results are compared to the ISS behavior. In this sense, the simulations are self-checking. However, even though this end-to-end verification approach is very powerful, implementation bugs deep in the core could be difficult to stimulate and may take a very long time to propagate to the outputs where they can be observed. To improve observability, Tensilica used a white-box verification methodology for the original development of the Xtensa IV processor core, which included Questa® Check and the CheckerWare® Library. The Mentor Graphics O-In Verification Business Unit tools were able to integrate seamlessly into Tensilica’s highly configurable verification environment.

Checkers Capture Assumptions

“The CheckerWare Library really helps us out because it gives us predefined checkers that the designer can use to capture the assumptions he is making while writing the RTL code. Checkers are very extensible and flexible so it is easy for us to use and enhance the CheckerWare Library,” said Dhanendra Jani, in charge of verification at Tensilica.

This approach enabled maximum design checking with minimal specification. Clocks, reset signals and activation conditions were automatically inferred from the RTL code by Questa Check. Additional checkers were automatically generated by Questa Check based on analysis of the RTL.

Checkers Ease Debugging

Many design flaws are buried deep inside a typical SoC design, and are invisible to traditional black-box simulation. To observe all the design flaws, it is not sufficient to simply apply stimulus at the inputs of a complex design and then check results at the outputs. In Questa’s white-box environment, checkers can be embedded in the internal RTL structures of the design, improving observability and documenting design assumptions. With this approach, whenever there is a violation in simulation, the checkers will fire and point out the source of the problem.

“By placing checkers on internal RTL structures, you can catch bugs in these areas immediately, even if the simulation test suite doesn’t propagate the effects of the bugs to the outputs,” said Mr. Jani. “Each design flaw or inconsistency that we found in the initial development of the Xtensa processor would have otherwise taken several hours to diagnose and fix. With Questa checkers and their debugging capability, we have done it in a matter of minutes.”

Documenting the Processor Interface

The Xtensa Processor Interface (PIF) is a sophisticated bus connecting the processor to the core integrator’s logic. The CheckerWare Library provides the necessary building blocks for users to build customer-specific checkers and monitors. Using Questa checkers, a PIF monitor was written to check all Xtensa processor interface protocol rules. “We created a custom protocol monitor with Questa checkers for our PIF. This monitor checks the bus protocol on the pins of the Xtensa core. During core verification, this monitor helped us document the interface and reduced debugging time,” commented Kaushik Sheth, chief engineer at Tensilica.

The checkers in the PIF monitor are embedded in the cores that Tensilica ships. By shipping the PIF monitor with the Xtensa core, Mr. Sheth said, “our customers can debug their interfaces in a much faster way rather than worrying about problems in the interface. They can focus more on integrating at the chip level and worry more about system level verification issues rather than how to interface to the core.”

Adapting to the Customer’s Implementation

When the Xtensa core is integrated with the customer’s logic, the checkers transparently provide an implementationspecific verification environment. Any violation of the processor interface logic can be identified immediately. The checkers reduce core integration time, chiplevel verification time, and cost of support for Tensilica. Customers are more confident that they are using the core the way it was intended. “We want to ensure that we deliver thoroughly verified intellectual property to our customers,” said Mr. Sheth. “That is why we embed Questa checkers in the cores that we ship. Our customers can then focus on integrating the core rather than debugging their interface logic.”

Results

“Questa products made us more productive and shortened our verification cycle. But more importantly, by embedding the checkers in the Xtensa core interface, we achieve our goal to deliver thoroughly verified, easily-integrated intellectual property to our customers,” continued Mr. Sheth. “As a result, our customers can have the highest degree of confidence in both the core and the interface.”

 
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