Questa and the OVM facilitate Xsigo’s move to a constrained-random verification methodology, efficiently delivering higher verification productivity and design quality and helping them to attain their goal of a robust, cutting-edge FPGA on time.
“It’s a losing battle if you try to write everything directed. Constrained random increases productivity, because you use [Questa] more instead of expending a lot of expensive engineering time. It’s much more powerful letting it manage the test for you.”
Mokammel Hoque, Verification Manager, Xsigo
FPGA projects, once limited mostly by FPGA capacity, today can rival ASICs in size and complexity. As validating and debugging FPGA designs in-circuit became impractical, Xsigo began looking for more sophisticated verification tools and technologies. To achieve top-to-bottom verification, Xsigo also wanted to port whatever they used at the block level to the system level, and vice versa. The bottom line: Xsigo wanted to preserve credibility with its customers by catching all critical bugs.
Xsigo settled on Questa and an efficient flexible OVM methodology, providing numerous automation and coverage features. The OVM helped to meet Xsigo's need for easy top-to-bottom verification this through its scalable, modular infrastructure and SystemVerilog transaction models. The combination of SystemVerilog assertions (SVA) and Questa was a boon, too. The Xsigo team used SVA to monitor areas of the design identified as high risk in their verification plan. They then used Questa to validate the assertions; if a failure occurred, the assertion would fire during simulation. Because the assertions were located near or at the point of failure, they immediately knew exactly where and when the error occurred, significantly reducing debug time.
By using this advanced verification environment, if there are scenarios that fail in-circuit, Xsigo can reproduce them in simulation and fix the bugs 100 times faster than they could in-circuit. Krishna Srinivasan, a Senior Verification Engineer at Xsigo, hailed the easy integration with Xsigo's existing verification environment, made possible by the OVM. "It’s plug-and-play," he says. "With a single suite you can run the exact same test you ran on first-level issues on second-level issues; you can use the exact same parameter, the exact same configuration."
“The OVM environment is flexible enough that you don’t have to maintain multiple environments.”
Uttam Aggarwal, Senior Verification Engineer, Xsigo
STMicroelectronics: Simulation + Emulation = Verification Success
Developing an ARM-based reference design, STMicroelectronics engineers linked a testbench running on a simulator with a design executed on an emulator, taking advantage of the best of both verification...
Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.