Testbench Automation

  • Constrained-random stimulus generation capabilities in SystemVerilog or SystemC greatly improve productivity
  • Powerful testbenches allow the creation of many more test vectors than would be possible with directed test techniques
  • SystemVerilog testbenches can be used to drive VHDL designs as well as SystemVerilog designs
  • SystemVerilog and SystemC testbench-specific features allow the creation of reusable testbenches and race-free interactions with the DUT

Testbench Automation - Verification Productivity


Products

  • Questa AFV (Advanced Functional Verification)

    Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.

  • Questa SV (SystemVerilog)

    The first SystemVerilog, single-kernel verification environment wth a constraint solver, an assertion engine, functional coverage and a common user interface.  Questa SV also provides a complete SystemVerilog design environment and built-in support for testbench automation (TBA), coverage-driven verification (CDV), and assertion-based verification (ABV).

  • inFact (Intelligent Testbench Automation)

    inFact testbench synthesis provides a straightforward way to achieve higher coverage, while significantly reducing input code required to write a testbench.

  • Questa Codelink
    Questa Codelink is a graphical source-level debugger for code executing on RTL processor models from ARM and MIPS.
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