inFact (Intelligent Testbench Automation)

inFact intelligently generates simulation sequences, data, and checks from a concise behavioral description of a design's specification, achieving high functional coverage at the module, subsystem, and system levels - resulting in a 10x gain in overall verification productivity.

 

Intelligent Testbench Automation

Mentor Graphics' inFact testbench automation solution is the first to use intelligent algorithms to synthesize meaningful testbench sequences while allowing the user to set verification goals prior to simulation and determine verification priorities.

The inFact algorithms rapidly generate test sequences, data, and checks on-the-fly during simulation, achieving the highest levels of functional coverage and early detection of design bugs. Unlike other testbenches technologies, inFact understands exactly what functionality, at any point in time, has been tested, enabling it to continuously target untested functionality. As a result, engineers using inFact can cut manufacturing re-spins, reduce the time spent in verification, and prevent tapeout delays caused by functional errors. 

Features

• Reduces input for creating testbenches for functional verification
• Enables reuse of 95% or more of input code from one design to the next
• Retargets testbenches at various levels of a design (module, subsystem, and full system)
• Redirects testbenches to achieve different goals based on verification needs at that specific time
• Reduces manufacturing respins that escape the verification process

Language Support

Simulation tasks in inFact are written in Verilog, SystemVerilog, C/C++, or SystemC – engineers are not required to learn a new language. Testbench sequences created by inFact contain stimulus and checks, and trigger assertions – in the same way other testbench techniques do. inFact works with the industry-standard simulators, including Questa, ModelSim, and others.