FV Technical Publications

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Accelerated Verification of a MATLAB-Driven Digital FIR Filter RTL Design Using Veloce and TBX

Posted in: Emulation Systems

This paper explores the verification of DSP and communication system Systems-on-Chip (SoC’s) using a typical signal processing system subsystem - in this case a very large parallel digital FIR filter - using MATLABTM from The MathWorks in an interoperable manner with a very high performance emulation system. The results are presented here using Mentor Graphics’ Veloce emulator and its TestBench Xpress (TBX) SceMi2.0 compliant transaction-based hardware acceleration application. The complete verification system architecture consists of a testbench comprised primarily of MATLAB calls made from a SystemC main program to an "engine" provided by The MathWorks. This engine is a separate process created at system initialization time by the SystemC program, and all but the design DUT and three transactors run on the Veloce host computer. Data is sourced and retrieved to and from the engine via calls made available in the engine's API. The data is created, processed, and displayed via string passing calls made from the SystemC to the engine. These strings are identical to MATLAB commands that are expected in the normal MATLAB console application. The signal stimulus provided by the testbench/MATLAB sub-system is delivered to the DUT via SystemVerilog DPI transactors running within TBX. Likewise, response vectors from the DUT are returned via another transactor to the testbench and the MATLAB engine for post-processing and display.

 

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Model-based Instruction Stream Generation for Processor Verification

This paper discusses a model-based approach to developing an instruction stream generator for modern microprocessor verification. Through the separation of concerns for several common instruction stream generation challenges, a robust and flexible framework is shaped for modeling complex concurrent processor behaviors and constraints, necessary to be able to generate valid and interesting instruction stream scenarios.

 

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A Closer Look at Veloce Technology: Taking Hardware-assisted Verification to the Next Level

Posted in: Emulation Systems

Chip and verification complexities continue to grow. Despite these growing complexities, time-to-market pressures require that chip verification be completed on schedule. Hardware-assisted verification is used primarily to reduce risk by running more verification in a given time. Successfully completing this type of verification depends on three main parameters: performance of the verification engine; quickly adopting the changes in RTL, IP, or peripheral interfaces; and emulating the behavior of the target environment. Ease-of-use, synergy with existing verification environments, and interoperability with software simulators are also contributing factors to successful hardware-assisted verification. This paper discusses the latest developments in Veloce’s™ highly optimized emulation SoC technology. It explores how Veloce’s unique architecture gives users the flexibility to build highly productive verification environments through the implementation of a hardware stimulus, a software stimulus, or a combination of the two.

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Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification

This paper will introduce the factory pattern, which has been used with parameterized classes as a proven technique for writing reusable verification class components, and it will provide examples along the way. We will provide guidelines for choosing when it is better to specify items statically with a type parameter versus dynamically with a factory configuration at runtime, and we will provide tips for structuring your class inheritance hierarchy using parameterized classes.
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Improving Efficiency, Productivity, and Coverage Using SystemVerilog OVM Registers

A subset of the currently used solutions will be described in this paper, followed by a list of register verification requirements, a description of some register testing styles and modes, along with a review of coverage modes and coverage goals and finally a short overview of such tools in use and the issues identified. The SystemVerilog [1] OVM [2] Register Package will be used to illustrate various techniques for verification and its API described listed in the appendix.
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Is There a Future for SystemVerilog Interfaces?

The SystemVerilog interface is intended to be a powerful modeling construct for describing hardware interconnect in a very general manner that is applicable to both testbench and synthesizable RTL design applications. In this paper we argue that the SystemVerilog interface construct is inadequately specified, insufficiently powerful for real applications, and impossible to implement consistently in its current form. We then review the application areas that interfaces were intended to address, and propose some possible solutions for these shortcomings.
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Towards an Object-Oriented Design Methodology Using SystemVerilog

Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are more and more seriously considering language-based methodologies for parts of their designs. The introduction of the System Verilog (SV) language initiated a closer relationship between software and hardware descriptions and development tools. This paper presents synthesis recommendations and the corresponding synthesis methodology to develop object-oriented models with SV constructs for hardware system implementations.
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VPI for SystemVerilog Goes Dynamic

The SystemVerilog language supports a rich set of new data types and the ability to create very general data structures at runtime. VPI has historically had a runtime information model whose data objects were primarily static in nature. This paper examines a more robust information model adopted in the 2009 LRM for handling dynamic data. After reviewing the history of VPI and the current conceptual programming model, we will focus on class variables and objects and what mechanisms there are to track dynamic object lifetime and changes. We extrapolate to the broader set of dynamic data types, the remaining work, and open issues in completing the VPI information model and functionality.
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Mitigate Multi-Processor Synchronization Risks with Processor-Driven Verification

Multi-processor synchronization techniques are extensions of well established single processor,multi-threaded, software based synchronization techniques. These multi-processor synchronization techniques require a high level of concurrent visibility of both hardware and processor instruction logic. The risks of effective verification of multi-processor synchronization hardware and processor instruction logic can be best mitigated using a processor driven verification methodology and supporting tools. The stimulus must come from the processor in conjunction with the system level test bench. Debug tools must be non-intrusive and provide concurrent visibility of the hardware and processor state of all processors in a multi-processor design. Although the design challenges of multi-processor synchronization could fill a whole book, take a quick look at the problem to see the acute need for flawless functionality of the hardware and software synchronization logic.

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