FV Technical Publications
Evolving the Coverage-Driven Verification Flow
Over the past decade, coverage-driven verification has emerged as a means to deal with increasing design complexity and ever more constrained schedules. Among the benefits of the new methodology -- a dramatically expanded set of verification metrics and tools providing much improved visibility into the verification process. However, coverage-driven verification flows are still beset by challenges, includng how to efficiently achieve coverage closure. Matthew Ballance describes how inFact's coverage-driven stimulus generator is helping to respond to these challenges with unique algorithms that help to simultaneously target multiple independent coverage goals.
Static and Formal Verification of Power Aware Designs at the RTL Using UPF
The Unified Power Format (UPF) low power specification standard allows designers to explicitly specify the insertion of isolation cells and level shifters at the RTL. In this paper, Rudra Mukherjee and his colleagues demonstrate a technique that leads designers to places in the design that are prone to bugs related to multi-voltage paths. The power intent is specified by the user in UPF and includes specification of the power domains, system power states, switches, and other power management features. This information will be used by the tool to perform static lint checking related to power/voltage domain crossings that are normally very difficult to figure out from simulation data. Mukherjee and his coauthors also present formal verification techniques that can be automated by the tool to reduce the burden on the designer. These techniques involve generating assertions, which test the power control sequencing, check for invalid sleep mode transitions, and catch the race condition between the retention controls (e.g., save and restore) and design controls (e.g., clock, set, reset).
Accelerated Verification of a MATLAB-Driven Digital FIR Filter RTL Design Using Veloce and TBX
This paper explores the verification of DSP and communication system Systems-on-Chip (SoC’s) using a typical signal processing system subsystem - in this case a very large parallel digital FIR filter - using MATLABTM from The MathWorks in an interoperable manner with a very high performance emulation system. The results are presented here using Mentor Graphics’ Veloce emulator and its TestBench Xpress (TBX) SceMi2.0 compliant transaction-based hardware acceleration application. The complete verification system architecture consists of a testbench comprised primarily of MATLAB calls made from a SystemC main program to an "engine" provided by The MathWorks. This engine is a separate process created at system initialization time by the SystemC program, and all but the design DUT and three transactors run on the Veloce host computer. Data is sourced and retrieved to and from the engine via calls made available in the engine's API. The data is created, processed, and displayed via string passing calls made from the SystemC to the engine. These strings are identical to MATLAB commands that are expected in the normal MATLAB console application. The signal stimulus provided by the testbench/MATLAB sub-system is delivered to the DUT via SystemVerilog DPI transactors running within TBX. Likewise, response vectors from the DUT are returned via another transactor to the testbench and the MATLAB engine for post-processing and display.
Model-based Instruction Stream Generation for Processor Verification
This paper discusses a model-based approach to developing an instruction stream generator for modern microprocessor verification. Through the separation of concerns for several common instruction stream generation challenges, a robust and flexible framework is shaped for modeling complex concurrent processor behaviors and constraints, necessary to be able to generate valid and interesting instruction stream scenarios.
A Closer Look at Veloce Technology: Taking Hardware-assisted Verification to the Next Level
Chip and verification complexities continue to grow. Despite these growing complexities, time-to-market pressures require that chip verification be completed on schedule. Hardware-assisted verification is used primarily to reduce risk by running more verification in a given time. Successfully completing this type of verification depends on three main parameters: performance of the verification engine; quickly adopting the changes in RTL, IP, or peripheral interfaces; and emulating the behavior of the target environment. Ease-of-use, synergy with existing verification environments, and interoperability with software simulators are also contributing factors to successful hardware-assisted verification. This paper discusses the latest developments in Veloce’s™ highly optimized emulation SoC technology. It explores how Veloce’s unique architecture gives users the flexibility to build highly productive verification environments through the implementation of a hardware stimulus, a software stimulus, or a combination of the two.
Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification
Improving Efficiency, Productivity, and Coverage Using SystemVerilog OVM Registers
Is There a Future for SystemVerilog Interfaces?
Towards an Object-Oriented Design Methodology Using SystemVerilog
VPI for SystemVerilog Goes Dynamic
Mitigate Multi-Processor Synchronization Risks with Processor-Driven Verification
Multi-processor synchronization techniques are extensions of well established single processor,multi-threaded, software based synchronization techniques. These multi-processor synchronization techniques require a high level of concurrent visibility of both hardware and processor instruction logic. The risks of effective verification of multi-processor synchronization hardware and processor instruction logic can be best mitigated using a processor driven verification methodology and supporting tools. The stimulus must come from the processor in conjunction with the system level test bench. Debug tools must be non-intrusive and provide concurrent visibility of the hardware and processor state of all processors in a multi-processor design. Although the design challenges of multi-processor synchronization could fill a whole book, take a quick look at the problem to see the acute need for flawless functionality of the hardware and software synchronization logic.