Multi-processor synchronization techniques are extensions of well established single processor,multi-threaded, software based synchronization techniques. These multi-processor synchronization techniques require a high level of concurrent visibility of both hardware and processor instruction logic. The risks of effective verification of multi-processor synchronization hardware and processor instruction logic can be best mitigated using a processor driven verification methodology and supporting tools. The stimulus must come from the processor in conjunction with the system level test bench. Debug tools must be non-intrusive and provide concurrent visibility of the hardware and processor state of all processors in a multi-processor design. Although the design challenges of multi-processor synchronization could fill a whole book, take a quick look at the problem to see the acute need for flawless functionality of the hardware and software synchronization logic.

Power is the number one constraint impacting today’s electronic designs. The need to minimize dynamic and static power consumption creates unique verification challenges. A common low power design technique involves switching off certain portions of the design (power islands) when that functionality is not required to reduce leakage power and restoring power when that functionality is needed again. This creates the need to save and restore state information with retention flops and latches, and to ensure the power island returns to a known good state when powered up.

Verification of correct design functionality of power islands within the context of a power management scheme has traditionally been performed at the gate level, if at all. Defect rectification at this level is costly in terms of resource and design cycle. This paper discusses the application of innovative techniques to enable power-aware verification at the RTL with traditional RTL design styles and reusable blocks.

With power becoming a critical design constraint in the design environment, designers are utilizing advanced techniques to minimize power consumption in their designs. As a result, the RTL design is being extended to express the functionality of new cell types including retention cells, level shifters, and isolation cells. Some of these cells act like buffers powered by different supplies. Others, such as retention cells, can have complex functionality that requires specific sequences of control signals to achieve correct behavior. Traditionally, designers have had to explicitly specify the insertion of these cells, either with wrappers around existing RTL blocks, or through simulation command files that mimic their expected behavioral impact. Using command scripts to mimic behavioral implications creates real challenges in verifying the desired functionality: after incorporating all of the power-aware features, one cannot be sure that what is simulated is the same as what will be implemented.

This paper will discuss the various challenges related to state verification of low power designs. We will describe mechanisms by which a designer can easily automate the complex process of managing the state elements in a low power design. A Power Aware Verification flow and tool is described that automatically detects the registers, latches, and memories present in the user’s RTL. The power intent is separately specified using the Unified Power Format (UPF). We will illustrate easy-to-use techniques to map specific retention behaviors to particular registers. We will also show how the tool automates the burden of connecting power and logic control signals to the verification models - thus automating this tedious task.