FV Technical Publications

Effective Functional Verification Methodologies for DO-254 Level A/B and Other Safety-Critical Devices

This paper discusses advanced functional verification in the context of the mil-aero industry's DO-254 safety-critical assurance process for complex hardware electronics. Advanced functional verification methods are explained that can be beneficial in terms of safety assurance and productivity gains, benefiting both the design assurance goals of certification authorities as well as the hardware vendors themselves.
Download

More Techpubs

Want to select multiple Techpubs? Switch to list view

A Closer Look at Veloce Technology: Taking Hardware-assisted Verification to the Next Level

Posted in: Emulation Systems

Chip and verification complexities continue to grow. Despite these growing complexities, time-to-market pressures require that chip verification be completed on schedule. Hardware-assisted verification is used primarily to reduce risk by running more verification in a given time. Successfully completing this type of verification depends on three main parameters: performance of the verification engine; quickly adopting the changes in RTL, IP, or peripheral interfaces; and emulating the behavior of the target environment. Ease-of-use, synergy with existing verification environments, and interoperability with software simulators are also contributing factors to successful hardware-assisted verification. This paper discusses the latest developments in Veloce’s™ highly optimized emulation SoC technology. It explores how Veloce’s unique architecture gives users the flexibility to build highly productive verification environments through the implementation of a hardware stimulus, a software stimulus, or a combination of the two.

Download

Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification

This paper will introduce the factory pattern, which has been used with parameterized classes as a proven technique for writing reusable verification class components, and it will provide examples along the way. We will provide guidelines for choosing when it is better to specify items statically with a type parameter versus dynamically with a factory configuration at runtime, and we will provide tips for structuring your class inheritance hierarchy using parameterized classes.
Download

Improving Efficiency, Productivity, and Coverage Using SystemVerilog OVM Registers

A subset of the currently used solutions will be described in this paper, followed by a list of register verification requirements, a description of some register testing styles and modes, along with a review of coverage modes and coverage goals and finally a short overview of such tools in use and the issues identified. The SystemVerilog [1] OVM [2] Register Package will be used to illustrate various techniques for verification and its API described listed in the appendix.
Download

Is There a Future for SystemVerilog Interfaces?

The SystemVerilog interface is intended to be a powerful modeling construct for describing hardware interconnect in a very general manner that is applicable to both testbench and synthesizable RTL design applications. In this paper we argue that the SystemVerilog interface construct is inadequately specified, insufficiently powerful for real applications, and impossible to implement consistently in its current form. We then review the application areas that interfaces were intended to address, and propose some possible solutions for these shortcomings.
Download

Towards an Object-Oriented Design Methodology Using SystemVerilog

Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are more and more seriously considering language-based methodologies for parts of their designs. The introduction of the System Verilog (SV) language initiated a closer relationship between software and hardware descriptions and development tools. This paper presents synthesis recommendations and the corresponding synthesis methodology to develop object-oriented models with SV constructs for hardware system implementations.
Download

VPI for SystemVerilog Goes Dynamic

The SystemVerilog language supports a rich set of new data types and the ability to create very general data structures at runtime. VPI has historically had a runtime information model whose data objects were primarily static in nature. This paper examines a more robust information model adopted in the 2009 LRM for handling dynamic data. After reviewing the history of VPI and the current conceptual programming model, we will focus on class variables and objects and what mechanisms there are to track dynamic object lifetime and changes. We extrapolate to the broader set of dynamic data types, the remaining work, and open issues in completing the VPI information model and functionality.
Download

Mitigate Multi-Processor Synchronization Risks with Processor-Driven Verification

Multi-processor synchronization techniques are extensions of well established single processor,multi-threaded, software based synchronization techniques. These multi-processor synchronization techniques require a high level of concurrent visibility of both hardware and processor instruction logic. The risks of effective verification of multi-processor synchronization hardware and processor instruction logic can be best mitigated using a processor driven verification methodology and supporting tools. The stimulus must come from the processor in conjunction with the system level test bench. Debug tools must be non-intrusive and provide concurrent visibility of the hardware and processor state of all processors in a multi-processor design. Although the design challenges of multi-processor synchronization could fill a whole book, take a quick look at the problem to see the acute need for flawless functionality of the hardware and software synchronization logic.

Download

Advanced Verification of Low Power Designs

Power consumption due to leakage has become a major factor in the total power consumption equation for battery powered and sub-100 nm designs, compelling design teams to adopt various power management design techniques. Power gating is one of the most effective techniques for managing leakage power.

In addition, at sub-65 nm process nodes, different biasing techniques are being combined with power gating in order to minimize leakage power. Employing low power techniques, such as power gating and substrate biasing, gives rise to many thorny verification challenges. For example, are the power control sequences correct; is my biasing strategy functionally correct; do the “awake” portions of the design still function correctly when other domains are powered down; is adequate state information retained when state retention is employed; is the proper retention protocol followed; and is my isolation strategy functionally correct.

Download

Functional Verification of Low Power Designs at RTL

Power is the number one constraint impacting today’s electronic designs. The need to minimize dynamic and static power consumption creates unique verification challenges. A common low power design technique involves switching off certain portions of the design (power islands) when that functionality is not required to reduce leakage power and restoring power when that functionality is needed again. This creates the need to save and restore state information with retention flops and latches, and to ensure the power island returns to a known good state when powered up.

Verification of correct design functionality of power islands within the context of a power management scheme has traditionally been performed at the gate level, if at all. Defect rectification at this level is costly in terms of resource and design cycle. This paper discusses the application of innovative techniques to enable power-aware verification at the RTL with traditional RTL design styles and reusable blocks.

Download
1 2 3 4 ... 9