Scalable Verification Technical Publications Listing

Verification is quickly becoming the major bottleneck in the process of getting quality products to market. Many companies are now reporting that over 70% of their time and effort is devoted to functional verification, and all indications are that this number will continue to climb at a steady pace. In addition, over 50% of chip re-spins are due to functional problems. When additional re-spins are necessary, the number caused by incorrect functionality increases to over 80%. Verification is not only taking more time, but also its effectiveness is coming into question. In this white paper, we explore some of these issues and look at the major functions and components of a verification strategy. As Gary Smith of Dataquest has stated, the biggest advances in our industry have not come from tools, but from methodology. Tools are enablers, but to focus on the tools is to live in today's world with today's problems.

Binding SystemVerilog to VHDL Components Using Questa SystemVerilog offers a rich set of testbench automation capabilities, native assertions, and functional coverage. These features make SystemVerilog increasingly appealing to VHDL users who need to implement an efficient and effective functional verification methodology.

The Questa(tm) advanced verification environment offers native support of SystemVerilog, Verilog, and VHDL, making it easy to adopt SystemVerilog.

The flexibility provided by Questa's single kernel architecture enables VHDL users to easily attach SystemVerilog to existing VHDL components. The connection is made using the SystemVerilog bind function, which gives modules and program blocks access to both external ports and internal signals in the bound VHDL object. Among other things, you can use this capability to monitor VHDL functionality with SystemVerilog Assertions (SVA) or assess the functional coverage of VHDL designs.

Design verification is taking an increasing proportion of the SoC design cycle. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems. Running regression suites against the design can take up to several years of CPU time to complete. In this paper, we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system-level verification.

The advent of new technologies-such as constrained-random data generation, assertion-based verification, functional coverage, and formal property checking-has changed the way we see functional verification productivity. Simulation speed is no longer the primary benchmark on which a verification process should be evaluated. Although simulation continues to be the heart of any realistic verification methodology, an advanced verification process enables users to manage the application of the aforementioned technologies in a complementary way, providing confidence that the myriad corner cases of the design space have been covered.

The inspiration for many of the new language capabilities in SystemVerilog has come from proprietary hardware verification languages (HVL) such as Vera and e, especially the former.

Therefore, it is understandable that people may be prone to assume that the assertion and verification capabilities in SystemVerilog are identical to those of OpenVera. Although there are many similarities, the two languages are different. If they were identical, it would be possible to successfully compile and simulate Vera source code in any simulator that supports SystemVerilog.

Of course, this is not true, and anyone who believes otherwise will be unpleasantly surprised.

How SystemVerilog differs from OpenVera™ is the topic of this paper.

In this paper, we introduce Assertion-based Verification (ABV) and the four pillars of its methodology. These are fundamental technologies and methodologies that make the ABV process successful. Each pillar targets a different phase of the overall design process; and each has its own users and objectives. The four pillars are:

• Pillar 1: Automatic Assertion Check
• Pillar 2: Static Formal Verification
• Pillar 3: Simulation with Assertions
• Pillar 4: Dynamic Formal Verification

Design teams need to improve existing verification methodologies by utilizing tools that scale across design complexity and by adopting multiple levels of abstraction. Such a scalable solution enables engineers to do what they do today, only better, faster, and more often within the same time frame. This paper examines the details of how this approach improves upon current verification techniques.

This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins.

With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.

This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.

This paper describes the basic elements of low power design and verification and discusses how the Unified Power Format (UPF) along with innovative techniques enable power-aware verification at the register transfer level, using traditional RTL design styles and reusable blocks. The result is a multi-tool solution that can be used throughout the RTL to GDSII flow, applying consistent semantics for both verification and implementation.

With asynchronous clocks common place in today?s ICs, designers need a solution to verify that the design?s functionality is not impacted by the non-deterministic effects of metastability. This paper describes why metastability occurs in designs with asynchronous clocks and analyzes the various methods that designers use to verify that the design is resilient with respect to the effects of metastability. It discusses the efficacy of each of these methods and describes in detail the behavioral model of metastability that is used in Mentor?s clock-domain-crossing verification solution. It will further present a complete verification methodology describing how designers can use this accurate model of metastability in their RTL simulations and verify that the design correctly handles the effects of the unavoidable occurrence of metastability in silicon.

This paper discusses some of the most common business-level issues aerospace companies are struggling with when seeking compliance to DO-254. Combining knowledge from various perspectives, including certification authorities, consultants, tool vendors, and users, this paper provides perspectives on how companies can address these costly issues to improve their bottom line, as well as reap the benefits.

This paper introduces a process (consisting of a set of recommendations) for achieving static formal verification closure. This process complements existing simulation processes. Using formal to aid simulation-and using simulation to aid formal are common themes throughout our paper.

This paper discusses advanced functional verification in the context of the mil-aero industry's DO-254 safety-critical assurance process for complex hardware electronics. Advanced functional verification methods are explained that can be beneficial in terms of safety assurance and productivity gains, benefiting both the design assurance goals of certification authorities as well as the hardware vendors themselves.

The expressive power of SystemVerilog assertions (SVA) with local variables enables you to specify complex properties in a concise form (for example, properties involving data integrity). However, using local variables might result in unacceptable performance during simulation or formal verification if you do not take precautions when coding your assertions.

This paper provides a set of coding guidelines and a methodology for efficient SVAlocal variable use. Our guidelines allow you to take advantage of the expressiveness of SVAlocal variables while avoiding potential pitfalls that can result in reduced performance and capacity.

Verification management is one of the most important factors in today?s verification of silicon chips and SoC designs. This whitepaper highlights a number of invaluable features of the new Questa 6.3 verification management functionality and shows how they can improve the efficiency of any verification process. Employing even the most basic portions of these features yields significant value.

As designs get more complex and previously independent functions become integrated on a single chip, chips with multiple asynchronous clock domains are becoming the norm. Signals that cross between these domains called clock-domain crossings, or simply "CDCs") can result in metastable operation, which often causes intermittent chip failures that can go undetected until the chip is in the lab or even operating in the field. This is a serious risk to safe system operation (not to mention the long debug times and extensive costs associated with troubleshooting and fixing these difficult problems). This concern is driving a swift adoption of CDC verification tools even into military and aerospace companies.

This paper introduces the issues concerning CDC, how to verify CDCs to avoid inadvertent design failures, and how/why to use 0-In CDC on DO-254 projects (including what is needed for tool assessment).

As the number of enhancements to various Hardware Description Languages (HDLs) has increased over the past year, so too has the complexity of determining which language is best for a particular design. Many designers and organizations are contemplating whether they should switch from one HDL to another.

This paper compares the technical characteristics of three, general-purpose HDLs:

• VHDL (IEEE-Std 1076): A general-purpose digital design language supported by multiple verification and synthesis (implementation) tools.
• Verilog (IEEE-Std 1364): A general-purpose digital design language supported by multiple verification and synthesis tools.
• SystemVerilog: An enhanced version of Verilog. As SystemVerilog is currently being defined by Accellera, there is not yet an IEEE standard.

With the number of clock domains increasing in today's complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verification. After having a CDC test plan, an effective CDC verification methodology should include structural, protocol, and metastability verification. This ensures that CDC signals are handled reliably at the design stage, avoiding costly respins after they are fabricated. We will outline how these are applied to block-level and top-level RTL modules. We will describe a few common CDC violations and the techniques used to determine whether they are real design issues or not. Finally, we will summarize and highlight the results of applying this methodology to a few designs.

SystemVerilog introduces strong types on top of the existing weaker Verilog data type system that can provide an environment similar to VHDL. SystemVerilog also introduces many new types used by the software developer that are useful for verification. This paper introduces methodologies for taking advantage of SystemVerilog's type system for both the designer and verification engineer.

Clock domain crossings (CDC) continue to be a trouble spot for functional verification. With the number of clock domains increasing in today's complex system designs, the ability to thoroughly verify CDC has become even more important. Traditional methods have come up short in fully verifying and controlling metastability, the primary manifestation of CDC errors. Fortunately, new tools and methodologies are available to address these shortcomings.

In order to get a handle on this complex problem, this paper gives an overview of the causes and effects of metastability along with a review of the traditional strategies that have generally failed to fully address CDC problems. With this background in place, the paper progresses to a discussion of the techniques and methodologies required to successfully identify all CDC errors.

Finally, a practical solution is presented that has already been proven on real-world designs. The Mentor Graphics 0-In CDC solution integrates advanced verification engines with engineered methodologies. It provides a systematic and comprehensive way to ensure that

CDC is handled reliably at the design stage, thus avoiding costly redesign of fielded products.

This paper explains how the technologies and methodologies underlying the Mentor Graphics® 0-In® Formal Verification (FV) tool facilitate practical formal verification of IC functionality. 0-In Formal Verification includes the 0-In Search, 0-In Confirm, and 0-In Prove engines and uses assertion-based verification (ABV) to accelerate the discovery and diagnosis of design flaws during the verification process. The differences between the Mentor Graphics 0-In FV tool and FV tools supplied by other vendors are also described.

As the old adage goes "those who fail to plan, plan to fail." This is certainly true when it comes to successful verification, where experience repeatedly demonstrates that success depends on methodical, verification planning combined with systematic verification processes. In this paper, I propose a verification process that includes formal verification as a key component. I present a systematic set of steps as a formal testplan and a set of strategies for effectively integrating formal verification into your design flow.

For e users, Aspect Oriented Programming (AOP) is a known, good mechanism for modifying, adding, or inserting functionality to a class. Fortunately, these goals can be easily achieved using Object Oriented Programming (OOP) techniques in SystemVerilog. The difference isn't that great, so the learning curve presents a gentle gradient.

Via comparison and code examples, this paper shows how a Specman e user can easily modify an object using SystemVerilog OOP. First we'll review a few programming basics., then compare how e and SystemVerilog handle abstract factory patterns in order to demonstrate how easy it is to replicate the AOP functionality of e in SystemVerilog OOP. We'll conclude the paper with a complete plug-and-run OOP code example.

This paper describes an assertion-based methodology for the verification of platform-based designs and present examples of ARM-based SoC design projects where it has been successfully applied. Assertion-based verification increases the observability and controllability of the design during verification by combining assertions, simulation, and formal verification techniques.

Over the past several years, a great deal of effort has gone into the development and deployment of functional verification tools and technologies. However, logical and functional flaws continue to be the leading cause of design spins by a fantastic margin. Yet despite the best efforts of the EDA industry, the problem is getting worse. Between 2002 and 2004 the percentage of designs with functional errors has actually increased.

Current verification tools and technologies are not only failing but also falling further behind the pace of design innovation. In order to reverse this trend, we need to change the way we think about functional verification in general and how we evaluate verification productivity specifically. We need to open the door to a new methodology that represents real value, not merely the re-packaging of distinct and disparate tools.

An advanced verification methodology is made possible by the purposeful application of an integrated set of intelligent methodologies to functional verification. As embodied in the Questa platform from Mentor Graphics, this advanced verification methodology enables users to manage and implement powerful technologies in a complementary way, providing confidence that the myriad corner cases of today's increasingly complex designs are covered.

Several years ago advances in testbench automation enabled verification engineers to test more functionality by dramatically increasing the quantity of testbench sequences for simulation. Through clever randomization techniques, constrained by algebraic expressions, verification teams were able to create testbench programs that generated many times more sequences than directed testbench programs could. While actual testbench programming time savings and simulation efficiency were hotly debated topics, few argued that constrained random test generation did not generate orders of magnitude more testbench sequences.

However, addressing the testbench sequence generation challenge through quantitative means (i.e. "more" sequences) caused corresponding challenges during the simulation and debug phases of functional verification.The latest advances in intelligent testbench automation now enable large simulations to be automatically distributed across up to 1000 CPUs, extending non-redundant sequence generation to entire simulation server farms. This massive gain in efficiency is attributable to the inherent architecture of rule-graphs and new advanced traversal algorithms tuned for production applications.

Using a current benchmark as the basis for the content, this article describes a Questa/inFact solution in which a small engineering team was able to fully verify an SOC IP module design, in less time and with fewer resources, than with the best their current constrained random test solution. Rather than limiting test generation to random tests, inFact used several algorithms to generate intelligent test sequences for simulation. In the head-to-head comparison, the Questa and inFact solution discovered every design error found by the current toolset, plus several more. And by synthesizing and simulating only meaningful test sequences, Questa and inFact found the design bugs earlier in the simulation process, and with fewer simulation resources.

Design verification is taking an increasing proportion of the SoC design cycle. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems. Running regression suites against the design can take up to several years of CPU time to complete. In this paper, we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system-level verification.

This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins.

With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.

This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.

This paper describes the basic elements of low power design and verification and discusses how the Unified Power Format (UPF) along with innovative techniques enable power-aware verification at the register transfer level, using traditional RTL design styles and reusable blocks. The result is a multi-tool solution that can be used throughout the RTL to GDSII flow, applying consistent semantics for both verification and implementation.

The need for better testbenches has resulted in considerable investment in testbench-related R&D by the EDA industry. This has largely focused on improving the coding languages that engineers use to write their testbench programs. Language improvements have made a noticeable difference: one can write a significantly better testbench (in less time) with a state-of-the-art language such as SystemVerilog or SystemC than with Verilog. Unfortunately, the verification problem has been getting harder at the same time, because design complexity has continued to increase. The net result is that there is still a compelling need for major improvements in testbench technology.

With asynchronous clocks common place in today?s ICs, designers need a solution to verify that the design?s functionality is not impacted by the non-deterministic effects of metastability. This paper describes why metastability occurs in designs with asynchronous clocks and analyzes the various methods that designers use to verify that the design is resilient with respect to the effects of metastability. It discusses the efficacy of each of these methods and describes in detail the behavioral model of metastability that is used in Mentor?s clock-domain-crossing verification solution. It will further present a complete verification methodology describing how designers can use this accurate model of metastability in their RTL simulations and verify that the design correctly handles the effects of the unavoidable occurrence of metastability in silicon.

Based on our experience helping many design teams deploy assertions and formal verification, we recommend deploying ABV (including formal model checking) on the most salient verification hot spots in a design, following a seven-step, formal verification planning process. By focusing ABV on verification hot spots, a design team can adopt ABV incrementally as they continue to use their simulation-based methodology. This has the added benefit of minimizing the risks involved with adopting a new methodology while maximizing the return-on-investment.

This paper discusses some of the most common business-level issues aerospace companies are struggling with when seeking compliance to DO-254. Combining knowledge from various perspectives, including certification authorities, consultants, tool vendors, and users, this paper provides perspectives on how companies can address these costly issues to improve their bottom line, as well as reap the benefits.

This paper introduces a process (consisting of a set of recommendations) for achieving static formal verification closure. This process complements existing simulation processes. Using formal to aid simulation-and using simulation to aid formal are common themes throughout our paper.

This paper discusses advanced functional verification in the context of the mil-aero industry's DO-254 safety-critical assurance process for complex hardware electronics. Advanced functional verification methods are explained that can be beneficial in terms of safety assurance and productivity gains, benefiting both the design assurance goals of certification authorities as well as the hardware vendors themselves.

The expressive power of SystemVerilog assertions (SVA) with local variables enables you to specify complex properties in a concise form (for example, properties involving data integrity). However, using local variables might result in unacceptable performance during simulation or formal verification if you do not take precautions when coding your assertions.

This paper provides a set of coding guidelines and a methodology for efficient SVAlocal variable use. Our guidelines allow you to take advantage of the expressiveness of SVAlocal variables while avoiding potential pitfalls that can result in reduced performance and capacity.

Verification management is one of the most important factors in today?s verification of silicon chips and SoC designs. This whitepaper highlights a number of invaluable features of the new Questa 6.3 verification management functionality and shows how they can improve the efficiency of any verification process. Employing even the most basic portions of these features yields significant value.

As an alternative to the use of traditional programmatic approaches to verification, this article introduces the use of an automata-based approach. And, the benefits of such an approach extend significantly into verification of complex system designs.

The Mentor Graphics intelligent testbench automation technology enables verification engineers to re-use subsystem VIP modules for system-level verification, without the traditional pain and suffering. By cataloging the available subsystem VIP modules, and by managing and granting the system design's hardware resources during simulation, the inFact Intelligent Testbench Automation solution creates extremely dense system-level verification stimulus, providing maximum stress on the target design, without creating any unwanted illegal conditions

Existing testbench techniques offer various benefits. However, once a testbench is initiated, it runs open-loop, generating results and then reporting them to an engineer. In turn, the engineer analyzes the results, makes some modifications to the system, and runs it again - and then repeats the process. The process runs open-loop, requires human intervention, and the iterations can span weeks, or even months.

Most verification engineers consider the "learning testbench" to be a vision of the future. However, a new advanced closed-loop testbench automation system "learns" from both the DUT and the testbench modules during simulations. By combining concepts previously associated with compiler test automation and logic design synthesis, along with some innovative recently-patented technology, Mentor Graphics augments directed testing and constrained random testing with intelligent testing - a learning-based system that actively targets desired results, rather than merely reporting them.

Intelligent testbench automation enables design teams to leverage the benefits of common testbench languages while providing a next-generation level of automation that increases functional coverage, which in turn, reduces overall testbench programming. This new technology uses algorithms to automate generation of simulation sequences, data, and checks from a concise behavioral description of a design's specifications.

Intelligent testbench automation achieves a higher level of functional coverage at the module, sub-module, and system level and finds more bugs faster than traditional methods. When intelligent testbench automation is employed, project teams design with a higher level of confidence, design quality improves in a fraction of the time, and manufacturing respins are dramatically reduced.

Why do semiconductor integration and design productivity continue to track Moore's Law, while functional verification seems to lag behind? You'd think advances in verification technology would enable functional testing to keep pace with design complexity. Or is there a difference between the ways design and verification have been automated? Take a closer look.

SystemVerilog introduces strong types on top of the existing weaker Verilog data type system that can provide an environment similar to VHDL. SystemVerilog also introduces many new types used by the software developer that are useful for verification. This paper introduces methodologies for taking advantage of SystemVerilog's type system for both the designer and verification engineer.

Transaction level modeling (TLM) is an increasingly important tool for both designs and testbenches. Transaction level models are used to describe complex systems at a high level of abstraction, allowing designers to work through architectural issues before committing to low level details of a complete implementation. This paper defines what a transaction is in terms of four common system modeling metaphors and presents a transaction data model that can be used to store and retrieve transaction information.

Over the past several years, a great deal of effort has gone into the development and deployment of functional verification tools and technologies. However, logical and functional flaws continue to be the leading cause of design spins by a fantastic margin. Yet despite the best efforts of the EDA industry, the problem is getting worse. Between 2002 and 2004 the percentage of designs with functional errors has actually increased.

Current verification tools and technologies are not only failing but also falling further behind the pace of design innovation. In order to reverse this trend, we need to change the way we think about functional verification in general and how we evaluate verification productivity specifically. We need to open the door to a new methodology that represents real value, not merely the re-packaging of distinct and disparate tools.

An advanced verification methodology is made possible by the purposeful application of an integrated set of intelligent methodologies to functional verification. As embodied in the Questa platform from Mentor Graphics, this advanced verification methodology enables users to manage and implement powerful technologies in a complementary way, providing confidence that the myriad corner cases of today's increasingly complex designs are covered.

Design verification is taking an increasing proportion of the SoC design cycle. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems. Running regression suites against the design can take up to several years of CPU time to complete. In this paper, we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system-level verification.

This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins.

With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.

This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.

This paper describes the basic elements of low power design and verification and discusses how the Unified Power Format (UPF) along with innovative techniques enable power-aware verification at the register transfer level, using traditional RTL design styles and reusable blocks. The result is a multi-tool solution that can be used throughout the RTL to GDSII flow, applying consistent semantics for both verification and implementation.

With asynchronous clocks common place in today?s ICs, designers need a solution to verify that the design?s functionality is not impacted by the non-deterministic effects of metastability. This paper describes why metastability occurs in designs with asynchronous clocks and analyzes the various methods that designers use to verify that the design is resilient with respect to the effects of metastability. It discusses the efficacy of each of these methods and describes in detail the behavioral model of metastability that is used in Mentor?s clock-domain-crossing verification solution. It will further present a complete verification methodology describing how designers can use this accurate model of metastability in their RTL simulations and verify that the design correctly handles the effects of the unavoidable occurrence of metastability in silicon.

Based on our experience helping many design teams deploy assertions and formal verification, we recommend deploying ABV (including formal model checking) on the most salient verification hot spots in a design, following a seven-step, formal verification planning process. By focusing ABV on verification hot spots, a design team can adopt ABV incrementally as they continue to use their simulation-based methodology. This has the added benefit of minimizing the risks involved with adopting a new methodology while maximizing the return-on-investment.

This paper discusses some of the most common business-level issues aerospace companies are struggling with when seeking compliance to DO-254. Combining knowledge from various perspectives, including certification authorities, consultants, tool vendors, and users, this paper provides perspectives on how companies can address these costly issues to improve their bottom line, as well as reap the benefits.

This paper introduces a process (consisting of a set of recommendations) for achieving static formal verification closure. This process complements existing simulation processes. Using formal to aid simulation-and using simulation to aid formal are common themes throughout our paper.

This paper discusses advanced functional verification in the context of the mil-aero industry's DO-254 safety-critical assurance process for complex hardware electronics. Advanced functional verification methods are explained that can be beneficial in terms of safety assurance and productivity gains, benefiting both the design assurance goals of certification authorities as well as the hardware vendors themselves.

The expressive power of SystemVerilog assertions (SVA) with local variables enables you to specify complex properties in a concise form (for example, properties involving data integrity). However, using local variables might result in unacceptable performance during simulation or formal verification if you do not take precautions when coding your assertions.

This paper provides a set of coding guidelines and a methodology for efficient SVAlocal variable use. Our guidelines allow you to take advantage of the expressiveness of SVAlocal variables while avoiding potential pitfalls that can result in reduced performance and capacity.

Verification management is one of the most important factors in today?s verification of silicon chips and SoC designs. This whitepaper highlights a number of invaluable features of the new Questa 6.3 verification management functionality and shows how they can improve the efficiency of any verification process. Employing even the most basic portions of these features yields significant value.

As designs get more complex and previously independent functions become integrated on a single chip, chips with multiple asynchronous clock domains are becoming the norm. Signals that cross between these domains called clock-domain crossings, or simply "CDCs") can result in metastable operation, which often causes intermittent chip failures that can go undetected until the chip is in the lab or even operating in the field. This is a serious risk to safe system operation (not to mention the long debug times and extensive costs associated with troubleshooting and fixing these difficult problems). This concern is driving a swift adoption of CDC verification tools even into military and aerospace companies.

This paper introduces the issues concerning CDC, how to verify CDCs to avoid inadvertent design failures, and how/why to use 0-In CDC on DO-254 projects (including what is needed for tool assessment).

Why do semiconductor integration and design productivity continue to track Moore's Law, while functional verification seems to lag behind? You'd think advances in verification technology would enable functional testing to keep pace with design complexity. Or is there a difference between the ways design and verification have been automated? Take a closer look.

SystemVerilog introduces strong types on top of the existing weaker Verilog data type system that can provide an environment similar to VHDL. SystemVerilog also introduces many new types used by the software developer that are useful for verification. This paper introduces methodologies for taking advantage of SystemVerilog's type system for both the designer and verification engineer.

As the old adage goes "those who fail to plan, plan to fail." This is certainly true when it comes to successful verification, where experience repeatedly demonstrates that success depends on methodical, verification planning combined with systematic verification processes. In this paper, I propose a verification process that includes formal verification as a key component. I present a systematic set of steps as a formal testplan and a set of strategies for effectively integrating formal verification into your design flow.

Over the past several years, a great deal of effort has gone into the development and deployment of functional verification tools and technologies. However, logical and functional flaws continue to be the leading cause of design spins by a fantastic margin. Yet despite the best efforts of the EDA industry, the problem is getting worse. Between 2002 and 2004 the percentage of designs with functional errors has actually increased.

Current verification tools and technologies are not only failing but also falling further behind the pace of design innovation. In order to reverse this trend, we need to change the way we think about functional verification in general and how we evaluate verification productivity specifically. We need to open the door to a new methodology that represents real value, not merely the re-packaging of distinct and disparate tools.

An advanced verification methodology is made possible by the purposeful application of an integrated set of intelligent methodologies to functional verification. As embodied in the Questa platform from Mentor Graphics, this advanced verification methodology enables users to manage and implement powerful technologies in a complementary way, providing confidence that the myriad corner cases of today's increasingly complex designs are covered.

This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins.

This document describes how to verify Actel FPGA designs using FormalPro. Specifically, the flow available in FormalPro is for Actel A54SX, A54SAX, Axcelerator and ProASIC family designs implemented with Precision RTL and Actel Designer. You can use FormalPro to verify other families of Actel devices; however, this verification flow has been used primarily for designs targeted to the above.

As ten, twenty, thirty million gate designs and larger become increasingly commonplace, traditional verification methodologies are rapidly becoming inadequate. In the wake of 90-nanometer and smaller geometries, this only becomes more severe. The designs that these technologies enable will include chips exceeding 70 million gates. And it will not be long before 200 million gate designs are ubiquitous. These designs will also contain individual blocks that are larger than the largest full chips many companies design today.

This document describes how to verify Xilinx FPGA designs using FormalPro. Specifically, the flow available in FormalPro is for Xilinx Virtex II designs implemented with Synplify-Pro and Xilinx ISE. You can use FormalPro to verify other families of Xilinx devices; however, this verification flow has been used primarily for designs targeted to Xilinx Virtex II.

This document describes how to verify Xilinx FPGA designs using FormalPro. Specifically, the flow available in FormalPro is for Xilinx Virtex family designs implemented with Precision RTL and Xilinx ISE. You can use FormalPro to verify other families of Xilinx devices; however, this verification flow has been used primarily for designs targeted to Xilinx Virtex II.

Despite significant advances in the scope and sophistication of EDA tools, the percentage of design respins caused by functional errors is rising. This problem is due in part to escalating system complexity and in part to the increased use of third-party intellectual property. To meet this challenge, more verification is required for virtually every design size. It is also required throughout the design cycle. Some means must be found to keep continuous, interactive verification from slowing down the design process.

Design verification is taking an increasing proportion of the SoC design cycle. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems. Running regression suites against the design can take up to several years of CPU time to complete. In this paper, we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system-level verification.

This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins.

With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.

This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.

Over the past several years, a great deal of effort has gone into the development and deployment of functional verification tools and technologies. However, logical and functional flaws continue to be the leading cause of design spins by a fantastic margin. Yet despite the best efforts of the EDA industry, the problem is getting worse. Between 2002 and 2004 the percentage of designs with functional errors has actually increased.

Current verification tools and technologies are not only failing but also falling further behind the pace of design innovation. In order to reverse this trend, we need to change the way we think about functional verification in general and how we evaluate verification productivity specifically. We need to open the door to a new methodology that represents real value, not merely the re-packaging of distinct and disparate tools.

An advanced verification methodology is made possible by the purposeful application of an integrated set of intelligent methodologies to functional verification. As embodied in the Questa platform from Mentor Graphics, this advanced verification methodology enables users to manage and implement powerful technologies in a complementary way, providing confidence that the myriad corner cases of today's increasingly complex designs are covered.

The Open Verification Methodology promotes a well defined SystemVerilog transaction-level interface, inviting integration of a host of verification technologies. Firmware has proven effective for functional verification of embedded hardware, so it follows that OVM integration of a firmware execution environment will advance the verification of embedded systems. To this end, Mentor Graphics has added OVM-compliant interfaces to the Seamless® HW/SW co-simulation tool. This article covers the firmware execution modes, supported processors, and interface points of the Seamless/OVM integration.

Design verification is taking an increasing proportion of the SoC design cycle. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems. Running regression suites against the design can take up to several years of CPU time to complete. In this paper, we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system-level verification.

The emergence of affordable high-end FPGAs is making them the technology of choice for an increasing number of electronics products that previously were the exclusive domain of ASICs. Offering unprecedented levels of integration on a single chip, today's programmable devices have widely expanded the size, scope, and range of applications that can now be deployed on them. To ensure a fast and efficient implementation of these advanced, feature rich FPGAs, designers need access to the latest in productivity enhancing electronic design automation (EDA) tools and methodologies. For years, hardware/software (HW/SW) co-verification has been commonly used to debug ASIC SoC designs. Now, with embedded processors such as the PowerPC405 from IBM, combined with multi-million gate capacities commonplace in Virtex series FPGAs, there is an increased relevance for ASIC-strength methodologies such as co-verification to add value in the FPGA design space.

Hardware software co-verification tools allow a designer to run software against a hardware design before a prototype has been built. They accomplish this by executing the software on a logic simulation of the hardware design. However, logic simulations are notoriously slow, typically running at about 1 to 10 clock cycles per second on complex designs. Co-verification tools mitigate this slowness by running only a small fraction of the bus cycles generated by the software against the simulated hardware. Most bus cycles, such as data references and instruction fetches, are executed against a simple memory array. This runs much faster and reduces the workload on the logic simulator. One consequence of this is that the "hidden" bus cycles are run without advancing time as far as the logic simulator is concerned. A problem occurs when the hardware has elements that depend on the clocks for proper operation, such as timers and counters.

Hardware/Software Co-Verification is typically performed at a low level of abstraction, using an Instruction Set Simulation (ISS) model of a CPU in conjunction with a Verilog or VHDL model of the rest of the design. This paper describes a higher level of software abstraction. The CPU subsystem will be replaced by an RTOS simulator and application code written to the Application Programmers Interface (API) of the RTOS. Verilog or VHDL is still used to model the rest of the design.

Memory address decoding is done by hardware while the software engineer relies on a specification to understand the memory map for a CPU. Similarly, Seamless must also rely on user input to understand how CPU addresses are mapped into physical memory devices. This application note describes a mechanism that is available to inform Seamless about complex address bit ordering.

To take advantage of the optimization features of the Seamless co-verification environment some of the memory models in the hardware design need to be replaced with ‘Seamless-ized’ versions. This application note describes how to use Denali Seamless memory models or how to edit your existing HDL memory models to work with Seamless.

When one thinks of co-verification, the image is of a team designing a system testing out its software on a virtual prototype of their hardware. So at first glance, a world-class designer of microprocessor cores like ARM would not seem a likely candidate for co-verification. But ARM thought differently. They saw the tremendous potential for co-verification in their design process and decided to use that in their latest processor design.

Instead of verifying custom software, ARM wanted to use co-verification to validate a new embedded core's ability to support Microsoft's Windows CE operating system before actually fabricating the core. This effort would take co-verification as far up the design cycle as possible, making this a highly interesting and challenging situation for all involved-ARM, Microsoft and Mentor Graphics (the EDA supplier of choice for the co-verification environment.)

This analysis allowed us to find critical performance bottlenecks in the software and hardware and identify the attributes of ARM-based systems which would efficiently deliver MPEG4 multimedia data streams.

This paper presents how STMicroelectronics used one part of the system-to-RTL flow, known as ‘RTL Platforms’, based on hardware/software co-verification, to reduce the development time of a complex multi-processor design. The device is a network termination or home gateway interfacing residential LANs to an ADSL access network.

A console is usually a terminal window connected via a serial line into an embedded system. It is used as a destination for printf() and putc() functions, and as a source for scanf() and getc() functions. Within the Seamless? Co-Verification tool, it is possible to implement stdin and stdout functionality in a manner well suited for a simulation environment.

The increasing complexity of embedded system design, combined with shorter product life cycles, and an intensified competitive landscape continues to push the limits of embedded design methodology. Complex designs contain more devices and, thus, greater interoperability. A strategy to resolve this complexity problem is to raise the level of modeling abstraction by working in higher-level, behavioral models written in C or HDL. This paper describes some of the benefits of working at this level of abstraction using a C-based design optimization and verification methodology.

With SoCs and embedded systems growing in complexity, being able to accurately predict the performance of a design becomes ever more complex and harder to accomplish. The ability to make an accurate assessment of a system's performance early in the design process allows designers to make architectural tradeoffs early on, reducing the risk of a redesign.

This paper will discuss a simulation-based virtual prototype methodology that helps designers accurately evaluate the performance of a design before committing to silicon. Through the use of an instrumented hardware prototype, designers will be able to capture and analyze profile data of the design's processors and system buses. As a result of this visibility, design teams will be able to optimize the performance of the design. This approach not only allows designers the ability to validate whether they have met their performance specifications, but also provides the opportunity to run "what-if analyses," allowing them to explore alternative design architectures.

Performance hotspots will be examined and alternative solutions to deal with bottlenecks such as hardware/software tradeoffs, software code changes, and alternative bus architectures will also be explored.

This article discusses three distinct methods of developing and executing processor-driven tests (PDT), which are test vectors driven into the design via the processor bus. For designs that incorporate or interface to an embedded CPU, PDTs can be a valuable addition to the functional verification test suite, because they can detect design errors that may be missed by more traditional HDL testbenches.

A long-standing collaboration between ARM and Mentor has produced an excellent silicon IP/EDA tool combination that has aided designers in successfully completing hundreds of SoC designs based on ARM processors.  Read how the high-speed HW simulation capability increases productivity for verification and regression testing of complex SoC designs.

Over the past several years, a great deal of effort has gone into the development and deployment of functional verification tools and technologies. However, logical and functional flaws continue to be the leading cause of design spins by a fantastic margin. Yet despite the best efforts of the EDA industry, the problem is getting worse. Between 2002 and 2004 the percentage of designs with functional errors has actually increased.

Current verification tools and technologies are not only failing but also falling further behind the pace of design innovation. In order to reverse this trend, we need to change the way we think about functional verification in general and how we evaluate verification productivity specifically. We need to open the door to a new methodology that represents real value, not merely the re-packaging of distinct and disparate tools.

An advanced verification methodology is made possible by the purposeful application of an integrated set of intelligent methodologies to functional verification. As embodied in the Questa platform from Mentor Graphics, this advanced verification methodology enables users to manage and implement powerful technologies in a complementary way, providing confidence that the myriad corner cases of today's increasingly complex designs are covered.

Embedded systems often have performance bottlenecks, which prevent them from meeting their performance requirements. Designers may employ high performance processors or perform code modifications to meet these performance goals. We will explore techniques to profile the system. We present data that can be extracted from the profiles allowing designers to identify bottlenecks. Then we shall present ways to modify the design. Depending upon the cause it could be a change in arbitration logic, modification in the code to keep certain variables in the registers, changes to the data organization such as using global variables, in-lining code, or migration from software to hardware.

The tutorial will present real life examples. One of the case studies will be low bit rate speech encoders. We will walk our audience through several changes in the design and their impact. Finally, we shall show the tuned design achieving much lower frequency, saving power and cost.

The growth in the system-on-chip (SoC) market is fueled by the need to increase performance and reliability while reducing overall system costs. This is exemplified by the recent introduction of Xilinx’s newest FPGAs, the Virtex-4 family.

ASIC-style integration and performance is now available in programmable logic. This means that FPGA designers need access to newer electronic design automation (EDA) tools and methodologies to maintain design efficiency and productivity. Hardware/software (HW/SW) co-verification is an example of one ASIC methodology that has recently gained relevance for platform FPGAs. In this article, I will introduce the concept of co-verification, and will describe its role, relevance, and realizable benefits in the context of programmable systems. I will also explain the actual development work done in cooperation with Mentor Graphics to extend existing IBM PPC405 HW/SW co-verification solution to more effectively target Xilinx devices.

Embedded systems rely on a close, integrated relationship between software and hardware. However, in a traditional embedded systems design cycle, hardware and software are often developed separately, then integrated after the hardware has been