Multiple Workstation Equivalence Checking Provides Capacity and Performance for Regression Testing of Multimillion Gate Designs.
|
Contributor: Kenneth Larsen, Mentor Graphics Format: PDF Document As ten, twenty, thirty million gate designs and larger
become increasingly commonplace, traditional verification
methodologies are rapidly becoming inadequate.
In the wake of 90-nanometer and smaller
geometries, this only becomes more severe. The
designs that these technologies enable will include
chips exceeding 70 million gates. And it will not be
long before 200 million gate designs are ubiquitous.
These designs will also contain individual blocks that
are larger than the largest full chips many companies
design today. |