Regression Testing: Gate-Level Functional Verification Is Imperative and Equivalence Checking Provides the Solution.
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Contributor: Ian Burgess Format: PDF Document Despite significant advances in the scope and sophistication
of EDA tools, the percentage of design respins
caused by functional errors is rising. This problem is
due in part to escalating system complexity and in part
to the increased use of third-party intellectual property.
To meet this challenge, more verification is required
for virtually every design size. It is also required
throughout the design cycle. Some means must be
found to keep continuous, interactive verification from
slowing down the design process. |