SV Technical Publications

Current techniques of applying test vectors from an HDL testbench only begin to mimic processor bus behavior. The introduction of processor driven testbenches into the existing verification methodology enables real-world verification and extensive re-use of testbench software throughout the project. One of the limitations to effective utilization of processor driven tests has been the difficulty debugging software in a processor running in a logic simulator. This paper presents proven methods of debugging and trace technology which overcome the limitations to enable the benefits of processor driven tests throughout various hardware and software integration stages of your project.

This document provides information for existing users of the Advanced Verification Methodology (AVM) users or people familiar with the AVM to begin using the Open Verification Methodology. There are a few levels of compatibility available that we address

The Open Verification Methodology (OVM) provides a framework that includes both a methodology and code libraries that a verification engineer can use to build a testbench that is modular, interoperable, and reusable. The inFact® intelligent testbench automation tool allows the user to build testbench components whose activity is controlled by one or more rule graphs that define the verification scenarios and stimuli that are to be applied to the device under verification (DUV) or to one of its interfaces.

This application note describes how you would construct an inFact OVM component and include it within an OVM-based testbench. It is assumed that the user is already familiar with other aspects of the inFact tool, such as building the rule graphs, coverage objects etc. It is also assumed that the user has a good understanding of the OVM.

Intelligent testbench automation enables design teams to leverage the benefits of common testbench languages while providing a next-generation level of automation that increases functional coverage, which in turn, reduces overall testbench programming. This new technology uses algorithms to automate generation of simulation sequences, data, and checks from a concise behavioral description of a design's specifications.

Intelligent testbench automation achieves a higher level of functional coverage at the module, sub-module, and system level and finds more bugs faster than traditional methods. When intelligent testbench automation is employed, project teams design with a higher level of confidence, design quality improves in a fraction of the time, and manufacturing respins are dramatically reduced.

Existing testbench techniques offer various benefits. However, once a testbench is initiated, it runs open-loop, generating results and then reporting them to an engineer. In turn, the engineer analyzes the results, makes some modifications to the system, and runs it again - and then repeats the process. The process runs open-loop, requires human intervention, and the iterations can span weeks, or even months.

Most verification engineers consider the "learning testbench" to be a vision of the future. However, a new advanced closed-loop testbench automation system "learns" from both the DUT and the testbench modules during simulations. By combining concepts previously associated with compiler test automation and logic design synthesis, along with some innovative recently-patented technology, Mentor Graphics augments directed testing and constrained random testing with intelligent testing - a learning-based system that actively targets desired results, rather than merely reporting them.