SV Technical Publications
Effective Functional Verification Methodologies for DO-254 Level A/B and Other Safety-Critical Devices
Using inFact in an OVM Environment--An Application Note
The Open Verification Methodology (OVM) provides a framework that includes both a methodology and code libraries that a verification engineer can use to build a testbench that is modular, interoperable, and reusable. The inFact® intelligent testbench automation tool allows the user to build testbench components whose activity is controlled by one or more rule graphs that define the verification scenarios and stimuli that are to be applied to the device under verification (DUV) or to one of its interfaces.
This application note describes how you would construct an inFact OVM component and include it within an OVM-based testbench. It is assumed that the user is already familiar with other aspects of the inFact tool, such as building the rule graphs, coverage objects etc. It is also assumed that the user has a good understanding of the OVM.
The Use of Advanced Verification Methods to Address DO-254 Design Assurance
Achieving Quality and Traceability in FPGA/ASIC Flows for DO-254 Aviation Projects
With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.
This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.
The New Wave in Functional Verification - Intelligent Testbench Automation
Intelligent testbench automation enables design teams to leverage the benefits of common testbench languages while providing a next-generation level of automation that increases functional coverage, which in turn, reduces overall testbench programming. This new technology uses algorithms to automate generation of simulation sequences, data, and checks from a concise behavioral description of a design's specifications.
Intelligent testbench automation achieves a higher level of functional coverage at the module, sub-module, and system level and finds more bugs faster than traditional methods. When intelligent testbench automation is employed, project teams design with a higher level of confidence, design quality improves in a fraction of the time, and manufacturing respins are dramatically reduced.
Closing the Loop in Testbench Automation
Existing testbench techniques offer various benefits. However, once a testbench is initiated, it runs open-loop, generating results and then reporting them to an engineer. In turn, the engineer analyzes the results, makes some modifications to the system, and runs it again - and then repeats the process. The process runs open-loop, requires human intervention, and the iterations can span weeks, or even months.
Most verification engineers consider the "learning testbench" to be a vision of the future. However, a new advanced closed-loop testbench automation system "learns" from both the DUT and the testbench modules during simulations. By combining concepts previously associated with compiler test automation and logic design synthesis, along with some innovative recently-patented technology, Mentor Graphics augments directed testing and constrained random testing with intelligent testing - a learning-based system that actively targets desired results, rather than merely reporting them.
Applying Assertion-Based Formal Verification to Verification Hot Spots
Based on our experience helping many design teams deploy assertions and formal verification, we recommend deploying ABV (including formal model checking) on the most salient verification hot spots in a design, following a seven-step, formal verification planning process. By focusing ABV on verification hot spots, a design team can adopt ABV incrementally as they continue to use their simulation-based methodology. This has the added benefit of minimizing the risks involved with adopting a new methodology while maximizing the return-on-investment.