Hardware-assisted Verification for Efficient Validation of Multi-processor Based Designs
Contributor: Richard Pugh, Hans Multhaup
Format: PDF Document
The use of multiple processors in System-on-Chip (SoC) designs is gaining momentum as single processor solutions hit their limits in performance and bandwidth. As this trend continues, the challenges faced in verifying these multi-processor environments also increases, creating the need for effective verification solutions. In this paper a targeted approach is introduced using hardware-assisted verification to provide designers with an efficient, accurate, and high-performance solution for multi-processor, SoC-based verification.