Advanced SoC Debug Solution
Intuitive and powerful HW and SW debug solutions to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms
The Mentor debug solution maximizes performance, capacity and automation for the complete SoC design and verification cycle. Tightly integrated with Questa Simulation and Veloce Emulation, the solution includes the industry-leading Codelink product family for hardware and software debug, and the new Visualizer Debug Environment for testbench and hardware debug.
Benefits and Features
- High-performance, high-capacity debug environment available interactive and post-sim
- Improves debug productivity for embedded SW, transaction-level, testbench, RTL, gate-level and low-power design and verification
Codelink is an advanced debug toolset for functional verification of processor-based designs using your RTL or gate-level processor models. Codelink aids processor-driven verification by dramatically improving...
Verification Horizons Blog
An online forum to provide updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
ARM® Techcon Paper Report: How Microsoft Saved 4 Man-Months Meeting Their Coverage Closure Goals Using Automated Verification Management & Formal Apps
Few verification tasks are more challenging than trying to achieve code coverage goals for a complex system that, by design, has numerous layers of configuration options and modes of operation. When the...
Preparing for the Perfect Storm with New-School Verification Techniques
Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased from about 30 to over 120. In the same period, the average number of embedded processors found in an advanced SoC...