Advanced SoC Debug Solution
Intuitive and powerful HW and SW debug solutions to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms
The Mentor debug solution maximizes performance, capacity and automation for the complete SoC design and verification cycle. Tightly integrated with Questa Simulation and Veloce Emulation, the solution includes the industry-leading Codelink product family for hardware and software debug, and the new Visualizer Debug Environment for testbench and hardware debug.
Benefits and Features
- High-performance, high-capacity debug environment available interactive and post-sim
- Improves debug productivity for embedded SW, transaction-level, testbench, RTL, gate-level and low-power design and verification
Codelink is an advanced debug toolset for functional verification of processor-based designs using your RTL or gate-level processor models. Codelink aids processor-driven verification by dramatically improving...
Verification Horizons Blog
An online forum to provide updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
Understanding and Minimizing Study Bias
This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group Functional Verification Study (for a background on the study, click here). In this blog I...
Prologue: The 2014 Wilson Research Group Functional Verification Study
This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group Functional Verification Study. However, unlike my previous Wilson Research Group functional verification...