Advanced SoC Debug Solution
Intuitive and powerful HW and SW debug solutions to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms
The Mentor debug solution maximizes performance, capacity and automation for the complete SoC design and verification cycle. Tightly integrated with Questa Simulation and Veloce Emulation, the solution includes the industry-leading Codelink product family for hardware and software debug, and the new Visualizer Debug Environment for testbench and hardware debug.
Benefits and Features
- High-performance, high-capacity debug environment available interactive and post-sim
- Improves debug productivity for embedded SW, transaction-level, testbench, RTL, gate-level and low-power design and verification
Codelink is an advanced debug toolset for functional verification of processor-based designs using your RTL or gate-level processor models. Codelink aids processor-driven verification by dramatically improving...
Verification Horizons Blog
An online forum to provide updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
Is Gate-Level Simulation Still Required Nowadays??
A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so, does their silicon actually work? In his day (and mine), teams prepared...
From Tightly Coupled (Loosely Bolted) to Verification Convergence!
It’s my favorite time of year again—DVCon! And I believe that the DVCon 2015 technical program committee has put together one of the technically best DVCon’s in years. In this blog I plan on highlighting...