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Advanced SoC Debug Solution

Intuitive and powerful HW and SW debug solutions to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms

The Mentor debug solution maximizes performance, capacity and automation for the complete SoC design and verification cycle. Tightly integrated with Questa Simulation and Veloce Emulation, the solution includes the industry-leading Codelink product family for hardware and software debug, and the new Visualizer Debug Environment for testbench and hardware debug.

Benefits and Features

  • High-performance, high-capacity debug environment available interactive and post-sim
  • Improves debug productivity for embedded SW, transaction-level, testbench, RTL, gate-level and low-power design and verification



Codelink is an advanced debug toolset for functional verification of processor-based designs using your RTL or gate-level processor models. Codelink aids processor-driven verification by dramatically improving... View Product Overview

Visualizer Debug Environment

Intuitive and easy to use, Visualizer Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs. View Product Overview

Verification Horizons Blog

An online forum to provide updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Accellera Approves UVM 1.2

Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM).  In completing this effort, the UVM 1.2 Class Reference Document... View Blog Post

Getting More Value from your Stimulus Constraints

Verification engineers put lots of effort into writing and tuning constraints for random stimulus. It’s critical that the constraints correctly express the valid relationships between the stimulus variables.... View Blog Post

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