Verification Components

The complexity of today’s SoC verification environments often requires designers to spend valuable time building and verifying standards-based verification components. These verification components support SoC validation and verification throughout the entire electronics systems development process and complement EDA verification tools.

With our pre-verified, configurable, and reusable verification components, your verification teams can reduce their overall testbench development effort, giving them more time for testing your proprietary designs and functions.

Our verification components support the full range of today’s popular protocols and verification environments, so you can achieve the high productivity of SystemVerilog verification techniques. By facilitating and enhancing the application of the Open Verification Methodology (OVM), transaction-level modeling (TLM), and inFact intelligent testbench automation, Mentor Graphics verification components increase productivity even further.

Products

• Questa Multi-View Verification Components (MVC)
  
  

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  Using a single model, Multi-View Verification Components (MVC) deliver a scalable verification solution for popular protocols and standard interfaces, including stimulus generation, reference checking, and coverage measurements. MVC incorporates Mentor’s unique Multi-View technology, which bridges the gap between RTL, TLM, and system-level verification.
• Questa Verification Library (QVL)
  
  

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  The Questa Verification Library (QVL) is a comprehensive SystemVerilog assertion checker and monitor library, making it easier to adopt assertion-based verification (ABV). With built-in coverage measurements, QVL integrates into any coverage-based methodology. QVL is the only assertion library optimized for formal verification.

Related Products

• inFact intelligent Verification Components (iVC)
  Using a single model during simulation, inFact intelligent Verification Components (iVC) generate intelligent test sequences, data, and checks on-the-fly for popular protocols and standard interfaces. iVC also generates self-testing, systematic, cross-product, accelerated random, and targeted testbenches, helping you achieve coverage closure faster than any other testing technique.
• Seamless Processor Support Pack (PSP) 
  Processor Support Packs (PSP) make it possible for teams designing single or multi-processor SoC designs to have full visibility and control of software execution during simulation. Our PSPs integrate performance profiling, help detect and isolate HW/SW interaction errors, and enable teams to eliminate expensive hardware prototyping iterations.
• iSolve Solutions
  For hardware accelerated HW/SW verification, our iSolve solutions for multi-media, networking, and consumer designs integrate embedded processors and DSP for real-world testing of complex system designs prior to silicon.
• ADMS Communication Library (Commlib)
  Our analog/mixed-signal CommLib library of essential telecommunication simulation models enables design teams to jumpstart the development of system-level designs and the exploration of architectural variations.