The advent of new technologies—such as constrained-random data generation, assertion-based verification, coverage-driven verification, formal model checking and Intelligent Testbench Automation to name a few — have changed the way we see functional verification productivity.
An advanced verification process enables users to manage the application of these new technologies in a complementary way, providing confidence that the myriad corner cases of today’s increasingly complex designs have been covered. Therefore we have created the Verification Horizons newsletter to expand the Verification topics to provide concepts, values, methodologies and examples to assist with the understanding of what these advanced functional verification technologies can do and how to most effectively apply them.
In This Issue
- Software-driven testing of AXI bus in a dual core ARM system
Using Questa to check everything from protocol compliance to fabric performance
- Caching in on analysis
Describing Questa SLI, a new technology for verifying system-level interconnect in both simulation and emulation.
- DDR SDRAM bus monitoring using Mentor Verification IP
See how Mentor VIP can be used to monitor and check protocol behavior.
- Simulation + Emulation = Verification success
Mentor VIP simplifies integration of emulation into your verification environment.
- Life isn't fair. So use Formal
Questa CoverCheck can help you get to that hard-to-reach last 10% of code coverage.
- AMS verification for high reliability and safety critical applications
A primer on AMS verification terms.
- Assertions instead of FSMs/logic for scoreboarding and verification
Use SystemVerilog assertions to monitor, check and report bus behavior in an interface.
“David is an Eagle Scout and our troop's Senior Patrol Leader... I'm the Scoutmaster... What that really means is that David and I have to work together to make sure that the troop functions well as a unit...”
Tom Fitzpatrick, Editor and Verification Technologist
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Volume 9, Issue 3
Software-Driven Testing of AXI Bus in a Dual Core ARM System
Here we present an architecture for verifying proper operation and performance of a complex AXI bus fabric in a dual-core ARM processor system using a combination of SystemVerilog and C software-driven test techniques.
Specifically, we describe deployment of an advanced graph-based solution that provides the capability for checking full protocol compliance, an engine for continuous traffic generation, precise control and configurability for shaping the form and type of traffic needed to test the fabric.
Caching in on Analysis
The advent of heterogeneous, multi-processor systems with multiple caches sharing the same data has added significantly to the complexity of interconnect design and has prompted the development of cache coherent protocols such as AMBA(r) 4 ACETM and AMBA 5 CHITM. Questa SLI supports interconnect verification with a range of capabilities targeting interconnect verification for both simulation and emulation. These capabilities include testbench and instrumentation generation based on Questa VIP; stimulus targeting interconnect and cache coherency verification; and visualization and analysis techniques aimed at giving insight into system level behavior.
DDR SDRAM Bus Monitoring using Mentor Verification IP
Verifying and debugging DDR SDRAM memory designs is challenging because of the speed and complex timing of the signals that need to be acquired and debugged. We can reduce this complexity using the DDRx Questa VIP (QVIP) as a bus monitor. In general, the bus monitor's task is to observe, so it should be configured to be passive and not inject errors. A monitor must have protocol knowledge in order to detect recognizable patterns in signal activity. QVIP has all these features and thus can be a boon to any verification team.
Simulation + Emulation = Verification Success
According to the 2012 Wilson Research Group Functional Verification Study sponsored by Mentor Graphics, about a third of new chip designs target a feature size of 28 nm or less and contain more than 20 million gates, and 17% of all new designs are greater than 60 million gates. About 78% of all new designs have one or more embedded processors. These numbers should give some pause, particularly given the rule of thumb that verification complexity scales exponentially with gate count.
Life Isn't Fair, So Use Formal
A state-of-the-art, constrained-random simulation environment will achieve a fairly high level of coverage as a by-product of verifying the functionality of the design. It is typically expected to achieve >90% coverage quite rapidly. However, getting closure on the last few percent of the coverage bins is typically where the effort starts to balloon.
AMS Verification for High Reliability and Safety Critical Applications
Functional verification of digital systems is primarily concerned with verifying that the logic design at the algorithmic and RTL level conforms to specification, and as a final check, physical verification is performed to make sure that nothing in the automation went wrong. Verifying that the logic and its circuit implementation are correct are orthogonal problems.
Assertions Instead of FSMs/logic for Scoreboarding and Verification
This article demonstrates another option of implementing some monitors and scoreboards using SVA assertions hosted in SV interfaces. The basic concept involves using assertion statements along with functions, called from sequence match items, to collect the desired scoreboard information, to compare expected results to collected data, and to trigger covergroups. This concept is demonstrated using a UART transmitter as the DUT.