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Verification Horizons

Current Issue

Volume 10, Issue 3

In This Issue

Verification Horizons

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

Learn about VIP master APIs that could be reused to generate stimulus on a cache coherent interface without worrying about accessing the cache model and other testbench objects. View Journal Article

How design engineers can get verification engineers to stop complaining, and other advice. View Journal Article

UVM unified many of the older methodologies and is a culmination of many years of work. But many of the practices of yester years crept in. Using some of those practices can cause needless complication... View Journal Article

Handling resets on the fly in UVM environments can be accomplished if the testbench components are built with reset awareness as described in the article. View Journal Article

Questa UVM debug helped the TVS team channelize effort that was otherwise being unproductively spent in fixing verification environment issues towards more critical verification tasks like feature addition... View Journal Article

Volume 10, Issue 3

Volume 10, Issue 2

In This Issue

Well here I am again. Last time I talked about putting stuff together, and when I mean stuff, it turned out that the digital folks handed me an RTL and the analog dudes gave me a SPICE netlist. View Journal Article

Functional coverage plays a very important role in verifying the completeness of a design. However customizing a coverage plan for different chips, users, specification versions, etc. is a very tedious... View Journal Article

SystemVerilog provides a way called weightage constraints using which, one can implement dynamism in today’s verification components. Support for normal implementation of weight-age constraints is... View Journal Article

Developing UVM-based testbenches from scratch is a time consuming and error-prone process. Engineers have to learn object oriented programming (OOP), a technique with which ASIC developers generally are... View Journal Article

SystemVerilog has the concept of covergroups that can keep track of conditions observed during a simulation. View Journal Article

My 16 year-old son just came downstairs to my office (I’m blessed to work from home) to reboot our home network router so that our television could connect to the internet. View Journal Article

This is an overview of best practices for FPGA or ASIC design, assuming a traditional waterfall development process. View Journal Article

Debugging these modern class-based testbenches has been painful for at least two reasons. First, they are designed and built using object-oriented coding styles, macros, dynamic transactions, phasing and... View Journal Article

This article describes how incorporating LLI Questa verification intellectual property (QVIP) can yield a host of benefits, including faster, more flexible verification and easier debugging. View Journal Article

Emulators, like Mentor Graphics Veloce®, are able to run designs in RTL orders of magnitude faster than logic simulators. View Journal Article

Volume 10, Issue 2

Volume 10, Issue 1

In This Issue

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

The internet revolution has changed the way we share content and the mobile revolution has boosted this phenomenon in terms of content creation & consumption. Moving forward, the Internet of Things... View Journal Article

IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged and tested. View Journal Article

Because UVM/OVM are TLM-based, sequence and sequence items play vital roles and must be created in the most efficient way possible in order to reduce rework and simulation time, and to make the verification... View Journal Article

Questa inFact graph-based intelligent testbench automation provides just such a “bridge” for VHDL testbench environments. View Journal Article

I don't know how this came about, but the other day I got hired to do something called AMS Verification. It seems that there is this chip design that combines digital and analog stuff, and I was asked... View Journal Article

Being up against a tapeout deadline isn’t all that different from fixing a heating system before a winter storm hits. Although the stakes are different in these two scenarios, it’s ultimately... View Journal Article

Volume 10, Issue 1

Volume 9, Issue 1

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article

Volume 9, Issue 1

 
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