December - Volume 5, ISSUE 3
“...it occurred to me that relying on good solid work that others have done is often the key to productivity...since it lets us focus on what we need to and lets us avoid wasting time and resources...”
Tom Fitzpatrick, Editor and Verification Technologist
December 2009 Issue Articles
Evolving Your Organization’s ABV Capabilities
Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today’s FPGA and ASIC design teams. Very few project managers would disagree with this statement. In fact, an often cited 2004 industry study by Collett International Research revealed that 35 percent of the total ASIC development effort was spent in verification.  In 2007, a Far West Research study indicated the verification effort has risen to 46 percent of the total ASIC development effort.  Furthermore, these industry studies reveal that debugging is the fastest-growing component of verification, and that it consumes 52 percent of the total verification effort. Unfortunately, with the increase in verification effort, the industry has not experienced a measurable increase in quality of results. For example, the Far West Research study indicated that only 28 percent of projects developing ASICs were able to achieve first silicon success.
To make matters worse, the industry is witnessing increasing pressure to shorten the overall project development cycle. Clearly, new design and verification techniques, combined with a focus on maturing functional verification process capabilities within an organization (and the industry as a whole) are required.
Advanced Static Verification is Indispensible
Traditionally, simulation-based dynamic verification techniques — such as directed tests, constrained-random simulation, and hardware acceleration — have been the work horse of functional verification. As modern day SoC designs become more integrated, the only way to advance significantly beyond dynamic verification is to increase the adoption of static verification. Leading-edge design teams have been using static verification successfully for a long time. It has been used strategically by designers to improve design quality and to complement dynamic verification on coverage closure.
Static verification techniques help accelerate the discovery and diagnosis of design flaws during functional verification, reducing the time required to verify a design and simplifying the overall development cycle for complex SoC designs. In this article, we will summarize a variety of static verification techniques; including RTL lint, static RTL checks (which include low power structure verification and clock domain crossing verification), sequential formal checks, automatic formal applications, and assertion-based formal property verification.
Evolving the Coverage-Driven Verification Flow
Verification methodology has undergone dramatic changes over the past decade. The realization that larger and more-complex designs required more and more verification effort, coupled with shrinking schedules, spawned new languages specifically tailored for verification and tools intended to make the verification process more predictable and efficient. As best practices were identified, languages and methodologies were standardized, and a supporting ecosystem of tools developed leading to the emergence of the coverage-driven verification flow.
Verification of an Ethernet PHY DUT Using Questa MVC
The Ethernet Multi-view Component (MVC) is an OVM-based Verification Intellectual Property (VIP) that eases the verification process for interfaces defined in IEEE 802.3-2008, part of the family standards defining the Physical Layer (PHY) and Data Link Layer’s media access control (MAC) sublayer of wired Ethernet.
Ethernet MVC provides a SystemVerilog interface for hooking a design under test (DUT) at various interfaces:
- CGMII, XLGMII, XGMII, GMII and MII
- 100GBASE-R, 40GBASE-R, 10GBASE-R, 10GBASE-X, 10GBASE-W and 1000BASE-X (both serial and parallel mode)
- Auto-negotiation for backplane Ethernet
- Standalone PHY
- Management interface
- Non IEEE standards RTBI, RGMII and RMII
Breaking Your Own Code; A Design Engineer’s Perspective on Verification Using Questa and OVM
This article discusses, from a Design Engineer’s perspective, the ease and benefits of migrating to a Verification environment using Questa and OVM Methodologies from a traditional native testbench environment using HDL’s.
Considering the current economic constraint, today’s VLSI engineers need to wear multiple hats, right from architecture design, Implementation to Verification. Migrating from a customized Hardware design environment to a standard Hardware Verification environment may seem trivial, but considering the advanced features/ additional capabilities (as compared to HDL) within an Object Oriented Context provided by HVL such as SystemVerilog with the latest Verification Methodology/tools (Questa/OVM) certainly proved challenging but also beneficial.
SEmulation - Use your emulation board as a hardware accelerator for ModelSim SE
Today’s complex, multi-million gate SoC designs consume a lot of development time, and hence money, with every simulation, synthesis or place & route run. At the same time, the pressure to be profitable and early to the market shortens design cycles and leaves almost no margin for errors.
Simulation of large RTL-designs is computation and time intensive. Interfacing with other physical systems cannot be included easily into RTL-simulations and is therefore tested on rapid prototyping systems. Wouldn’t it be great if you could use your emulation platform as a hardware accelerator for your RTL-simulations and be able to quickly jump back and forth between the world of simulation and the world of emulation?
Gleichmann Electronics Research’s SEmulator® is such a bridge between the world of simulation and the world emulation.
Coding Concise SystemVerilog Assertions
The introduction of SystemVerilog Assertions (SVA) added the ability to perform immediate and concurrent assertions for both design and verification, but some engineers have complained about SVA verbocity or do not understand some of the better methodologies to take full advantage of SVA.
This article documents a valuable SVA trick to generate concise design assertions. The concise coding style detailed in this article can reduce concurrent SVA coding efforts by 50%-80% over conventional SVA coding techniques.
Methodology for Board Level Functional Simulation and Hardware/Software Co-Verification Using Seamless
As product designs become more complex and there is less time to deliver these complex designs, the importance of delivering a first-time correct design and earlier hardware/software integration is becoming a priority in the product design cycle. One way to achieve the goal of a first-time correct hardware design is to use board level functional simulation. The Mentor Graphics Seamless® co-verification tool can be used in the board level simulation environment to perform hardware/software co-verification before the first physical prototype boards arrive in the lab. This not only provides earlier hardware/software integration testing, but also provides earlier and greater visibility of any problems that may arise during that integration.
This paper describes:
- the objectives of board level simulation and hardware/software
- a verification flow and verification environment using Seamless
- different verification methodologies to address specific verification challenges
- lessons learned
- benefits derived and trade offs from employing a board level functional simulation and hardware/software co-verification methodology using Seamless