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Horizons Newsletter - February 2008

“Before we get started, I must confess that it’s a bit difficult to concentrate on this issue since I’m still depressed by the Patriots’ Super Bowl loss. But at least I have my job to help take my mind off the pain. Actually, one of my favorite jobs is editing this newsletter, because I’m always impressed by the quality of the technology I get to share with you. I hope you’ll share my excitement with this issue.

Our first article, “OVM: Open Interoperable Verification,” provides a more detailed description of some of the key features in the OVM that enable, promote, and encourage the development of reusable verification components and environments. It also provides an update on the status of the OVM which earlier this month received the IEC Design Vision award at DesignCon, and includes a link where you can find even more detail, an OVM discussion forum, and the OVM source code to download for free!

The product spotlight this issue focuses on our Questa inFact™ Intelligent Testbench Automation solution, continuing a series of articles introducing and explaining this exciting new technology. In “Intelligent Testbench Automation — Now a Reality, No Longer Just a Promise,” the Questa inFact team shows the results of a customer’s test case in which Questa inFact was compared against their established constrained-random methodology. I won’t spoil the surprise for you, so you’ll have to readthe article. But the words “order of magnitude” and “wow” come to mind.”

Tom Fitzpatrick, Editor and Verification Technologist

February 2008 Issue Articles

OVM - Open Interoperable Verification

The previous issue of Verification Horizons offered a brief introduction to the Open Verification Methodology (OVM), a joint development initiative between Mentor Graphics® and Cadence® Design Systems that provides the first open, interoperable, SystemVerilog verification methodology in the industry.

Built on the successful Advanced Verification Methodology (AVM) from Mentor Graphics and the Universal Reuse Methodology (URM) from Cadence, the OVM brings the combined power of these two leading companies together to deliver on the promise of SystemVerilog. This article presents more technical details about the OVM and provides an update on its status.

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Intelligent Testbench Automation - Now a Reality, No Longer Just a Promise

Using a combination of Questa Functional Verification and Questa inFact™ intelligent testbench automation, a small engineering team was able to fully verify an SOC IP module design, in less time and with fewerresources, than with the best their current constrained random test solution could offer.

Rather than limiting test generation to random tests, Questa inFact used several algorithms to generate intelligent test sequences for simulation. In the head-to-head comparison, the Questa and Questa inFact solution discovered every design error found by the current toolset, plus several more. And by synthesizing and simulating only meaningful test sequences, Questa and Questa inFact found the design bugs earlier in the simulation process, and with fewer simulation resources.

Like many others, this customer’s engineers moved to constrained random testing several years ago. But that solution continues to be limited to random test generation only, and also is confined to a proprietary language format. Using Questa and Questa inFact, the engineering team was able to use a combination of testbench self-test, systematic
functional test, and accelerated random test sequences - including applying a combination of these simultaneously to different parts of thedesign.

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Are You Missing Assertions?

Assertions, once used only by high-performance processor designs, are now regularly included as part of the verification strategy for both ASICs and complex FPGAs. Their many benefits are undisputed. Yet, to effectively incorporate assertions in a verification plan, a methodology is needed to determine if the set of assertions defined for the design is sufficient to cover its functionality.

In this article, we describe an assertion density metric based on the minimum sequential distance (MSD) between each sequential design element and an assertion in its fan-out. As such, it measures whether the functionality of the logic is covered by an assertion. This MSD assertion density metric should be made a key part of any verification plan aiming to support an assertionbased verification strategy and more proactively prevent bugs from escaping the verification process.

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Debugging Synchronization Failures in Multi-Core Designs

Synchronization problems in multi-threaded systems are relatively straight forward to debug and correct. While there are multiple threads which must share data and resources, in a single processor system there is only one execution stream. Execution of one thread is suspended while the core turns its attention to another thread. Execution transition from one thread to the next is managed by the RTOS, is deterministic and repeatable.

As a result, debugging data and resource conflicts between threads is straight forward. Multiple cores bring considerable complexity to a multi-threaded system. Now the threads are running in parallel, not in sequence, and the dynamic sharing of data and resources can result in synchronization errors that are challenging to decipher.

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FPGA Design and Verification in Mechatronic Applications

THE VHDL-AMS LANGUAGE IS AN UNDISCOVERED ASSET FOR FPGA DESIGNERS – A POWERFUL TOOL TO DEFINE AND VERIFY REQUIREMENTS IN A NON-DIGITAL CONTEXT

The value of modern systems, such as automotive and aerospace vehicles, has become heavily influenced by their electronic content. Consequently, selecting the right electronic components and choosing the optimal design methodology is vital in developing a successful product. The flexibility of new components, such as FPGA devices, is intriguing. The potential of these devices, however, cannot be fully (and safely) utilized without incorporating the latest design and verificationmethodologies.

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Migrating Ethernet VIPto OVM Is a Cinch

The Advanced Verification Methodology (AVM) was instrumental in delivering SystemVerilog to the masses. This was partly due to its open, interoperable format. In addition, it supplied models, instructions, and support that allowed verification and design engineers alike to take advantage of advanced verification technologies, including objectoriented programming, without having to be verification language experts. Today, the openness and benefits of the AVM have been expanded into the Open Verification Methodology (OVM). It is our good fortune that the transition from AVM to OVM is an easy one and can be made without any modification to existing code.

Even when standalone VIP is fully verified to be good, integration at the chip level is not a trivial task. Many VIP developers have not thought about the issues users face when they are using VIP at the chip level. Thus, VIP usage at the chip level should be a high priority as more and more VIP is moving from verification at the module level toward creating interesting scenarios at the chip level.

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