Februrary 2011 - Volume 7, ISSUE 1
“I was thinkingabout this idea of transformation — taking something familiar and adding a new twist that makes it better...”
February 2011 Issue Articles
SystemVerilog Testbench Acceleration with Co-Emulation
What’s driving today’s SoC design complexity? It’s today’s consumer demand for devices that handle more and more content— that include integrated digital, audio, and data—always on and connected—anytime, anywhere. In fact, today we are seeing that 78% of all new designs fall under the SoC category—containing multiple embedded processors, lots of internal and external IP reuse, and embedded software. Verification and validation of these devices, by nature, is complex.
A Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches
This is part 1 of a two-part article on this topic. Part 2 will appear in the DAC edition of Verification Horizons. This article should serve as a great companion piece to the new Verification Academy module, Acceleration of SystemVerilog Testbenches with Co-Emulation.
Improving Embedded Software Integration with Veloce Emulation and the Questa Codelink Debug Environment
Today’s system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers. Accordingly, leading semiconductor companies are looking to more closely integrate software development and validation with silicon design and verification. One obstacle to such integration addressed in this article, is the difficulty in effectively debugging early-stage embedded software. What follows is a description of a new software debugging methodology for software and system-level integration teams called Questa Codelink. When tied with Mentor Graphics Veloce hardware emulation platform, Questa Codelink reduces debug closure time and effort required to develop SoC firmware and device drivers.
UVM - The Next Generation in Verification Methodology
UVM is a new verification methodology that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to enable creation of robust, reusable, interoperable verification IP and testbench components.
Achieving Flawless UVM Testbench Creation
Perhaps you have created many testbenches and it is time to reflect on how you can improve the creation process based on your experiences and by adopting the UVM (Universal Verification Methodology). In order to achieve a flawless UVM testbench, you need a method to:
- Automate as many creation steps as possible
- If automation is not possible, have reliable advice readily available for every decision point
Mentor Graphics created Certe™ Testbench Studio specifically to help you create near-perfect testbenches every step of the way through your UVM testbench project. And, if you are utilizing AVM (Advanced Verification Methodology) or OVM (Open Verification Methodology), the tool supports those methodologies as well.
This article shows you how to approach creation perfection by using Certe Testbench Studio.
SystemVerilog Boot Camp
This article will discuss how within a short time, students learned a new set of Verilog constructs, and how to use them to solve specific problems. We started with 30 students, fresh graduates from 25 different schools, chosen to undergo a “Verification Engineer” training program as part of Mentor Graphics HEP (Higher Education Program) initiative. The task – use an NCSU (North Carolina State University) developed course to teach the chosen 30 students “SystemVerilog for Verification”, enabling them to find good jobs in the industry.
How Transactions Viewing Accelerates Debug of Asynchronous SystemVerilog Designs
This paper describes how Questa’s Verilog APIs for transaction recording and viewing, allow the designer to create an effective debug environment for asynchronous/clockless circuits utilizing Tiempo technology.
It first introduces how to write high-level synthesizable models of asynchronous circuits, and then shows how to use Questa’s Verilog APIs to record transaction streams and attributes. It finally illustrates how to debug clockless designs using those records. As a result, the designer can see how the design, simulation and debug of asynchronous circuits using Tiempo SystemVerilog coding style, together with the Mentor Graphics Questa transaction-based simulation environment is no more difficult than for conventional synchronous circuits.
Lessons in Developing and Deploying OVM Compliant VIP
Using external VIP (Verification IP) brings several advantages including availability, independence in both checkers and coverage, robustness from use in several environments. However, the VIP must be developed so that it is easy for the user to incorporate the VIP into their environment. In this paper we look at practical lessons learned in both the development and deployment of VIP for use in complex OVM (Open Verification Methodology) SoC (System-on-Chip) verification environments.
A Full Function Verilog PLL Logic Model
This paper describes the full function model of a phase locked loop (PLL) in a logic simulator. In contrast to conventional models that bypass the PLL function, this Verilog model accurately represents all major characteristics of a PLL.
It allows the simulation of the effect of the actual filter elements. It can accurately model clock deskew of a clock tree as well as synthesize other frequencies from the input clock. It produces a lock detect signal after a realistic lock sequence. The user has the option to add jitter to the PLL output. The model performs three orders of magnitude faster than an equivalent circuit model.
Document Driven Verification (DDV) - Ready to Throw Out Your Verification Plan?
Not having a good list of specifications for a large SOC design kills the project before it starts. The verification team, as the first customer of such a design, relies on the specs to build a set of realistic scenarios around the design. These scenarios comprise a verification world that is almost always bigger and more complicated then the design being verified. Accordingly, building this world often requires more effort and time than building the design itself.
Verification is not a linear or deterministic process. Theoretically we could verify forever and still not verify everything. Since schedules are always constrained and deadlines are a fact of life, decisions must be made to determine how to get the best and most verification done in the allotted time. To do this, successful verification teams think through and document their verification plan upfront, a difficult but ultimately worthwhile process.