February 2013 Issue Articles.
“As verification engineers, we have to be able to forecast the accurate completion of our projects and also be able to cope with problems that may occur. Unfortunately, there are severe consequences when we get it wrong.”
Tom Fitzpatrick, Editor and Verification Technologist
February 2013 Issue Articles
- Using Formal Analysis to 'Block and Tackle'
- Bringing Verification and Validation under One Umbrella
- The Evolution of UPF - What's Next?
- Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features
- SVA in a UVM Class-based Environment
- The Formal Verification of Design Constraints
- OVM to UVM Migration, or 'There and Back Again - A Consultant's Tale.'
Using Formal Analysis to 'Block and Tackle'
Traditionally, connectivity verification at the block level has been completed using dynamic simulation, and typically involves writing directed tests to toggle the top level signals, then debugging why signal values did not transition as expected. For modules with a high number of wires and many modes of operation, the number of required tests quickly becomes unmanageable.
Bringing Verification and Validation under One Umbrella
A unified flow for RTL verification and pre-silicon validation of hardware/software integration is accomplished by combining a mainstream, transaction-level verification methodology - the Universal Verification Methodology (UVM) - with a hardware-assisted simulation acceleration platform (also known as co-emulation).
The Evolution of UPF - What's Next?
UPF 2.1 is an incremental update of UPF 2.0, not a major revision. That said, UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. This article describes some of the more interesting enhancements and refinements coming soon in UPF 2.1.
Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features
Power management is a critical aspect of chip design today. This is especially true for chips designed for portable consumer electronics applications such as cell phones and laptop computers, but even non-portable systems are increasingly optimizing power usage to minimize operation costs and infrastructure requirements.
SVA in a UVM Class-based Environment
Verification can be defined as the check that the design meets the requirements. How can this be achieved? Many verification approaches have been used over the years, and those are not necessarily independent, but often complementary. For example, simulation may be performed on some partitions while emulation in other partitions.
The Formal Verification of Design Constraints
There are two approaches to the verification of design constraints: formal verification and structural analysis. Structural analysis refers to the type of analysis performed by a static timing tool where timing paths either exist or not based on constant settings and constant propagation. Formal verification, on the other hand, establishes the condition under which a timing path exists based on the propagation requirements for the path.
OVM to UVM Migration, or 'There and Back Again - A Consultant's Tale.'
While it is generally accepted that the Universal Verification Methodology (UVM) is the way forward for modern SystemVerilog based verification environments, many companies have an extensive legacy of verification components and environments based on the predecessor, the Open Verification Methodology (OVM).