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November - Volume 6, ISSUE 3

“It all comes down to building on the familiar while pushing the boundaries a bit and stepping a little outside your comfort zone.”

Tom Fitzpatrick, Editor and Verification Technologist

November 2010 Issue Articles

Survey Says - Verification Planning

As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce a new module focused on Verification Planning, which has been one of the Verification Academy’s mostrequested subjects for new content. The new Verification Planning module is delivered by our subject matter expert, who literally wrote the book on the subject, Peet James. The goal of verification planning and management is to architect an overall verification approach, and then to document that approach in a family of useful, easily extracted, maintainable verification documents that will strategically guide the overall verification effort so that the most amount of verification is accomplished in the allotted time. The aim of this module is to define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project. I think you will really enjoy and be enlightened by Peet’s treatment of the subject, and hopefully, you can apply many of the techniques that he presents to your own projects.

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Firmware Verification Using SystemVerilog OVM

Semiconductor design is changing rapidly, which in turn forces continual evolution of verification methodologies and languages. This change is happening across the board, affecting not only expensive chips bound for big-iron servers but also more modestly priced processors built for specific applications.

Consider the case of embedded microcontrollers. These integrated blocks of processing capability, memory and programmable peripherals are found in a range of products, from power tools to toys. Their reach is in part due to their plunging cost. Today, 8-bit microcontrollers, which account for the majority of all CPUs sold in the world, sell for as little as $0.25 each. Consider that in the early 1970s, Intel’s 8008, the world’s first 8-bit processor, sold for $120, an amount roughly equal to $520 today.

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A SystemVerilog Configurable Coverage Model in an OVM setup

With the advent of a new era in verification technology based on an advanced HVL like SystemVerilog, the concept of random stimulus based verification was born, to verify today’s multi-million gate designs.

In concept, every verification engineer fancies the idea of random stimuli driven verification, but as is rightly said – “Everything comes with a cost” and the cost here is a big concern that haunts the life of every verification engineer:

  • How do I close my verification?
  • When can I say I am done?

To answer such questions, SystemVerilog as a language came up with the concept of Functional Coverage that is much more accurate of a measure compared to the traditional Code Coverage techniques. We concentrate mainly on this SV feature in our write-up, adding one more dimension to it - configurability.

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Advanced Techniques for AXI Bus Fabric Verification

AXI bus fabric verification presents many challenges. These arise due to the inherent complexity of the fabrics themselves, plus the challenges of developing a verification environment having the necessary verification components. The problem is further complicated by schedule pressures to finish the verification work quickly, when the actual development and debug of significant portions of the environment are gated by the availability of fabric RTL having basic functionality.

This article presents a number of techniques and strategies for AXI bus fabric verification to address these problems and provide a more comprehensive verification solution. Figure 1 shows a traditional approach for AXI fabric verification contrasted with an approach that employs a virtual AXI DUT fabric and algorithmic test generation techniques.

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Converting Module-Based Verification Environments to Class-Based Using SystemVerilog OOP

The technology industry keeps on changing the approach of verification to save verification cycles and to make it more flexible for the user. However this kind of change is infrequent and requires a significant amount of time before it is adopted by the majority of users. Even so, it is always difficult for the verification engineer, who must adopt a new verification approach and change code that is invested with a massive amount of work.

This becomes an urgent requirement when its user demands the same with the new approach. There are two options:

  1. Recode everything with the new approach or
  2. Wrap the existing code with another layer which uses the existing code inside but provides the user with a new environment that follows the new verification approach.

This paper provides a model (using option 2) where a module based test environment can be transformed into a class based environment by the use of an object orientated concept of SystemVerilog.

This paper discusses a very efficient approach where a layer of class is built around modules and everything which is visible to the outside world is a class. The advantage of a class based environment is that the user can build their own environment over the existing one using an object orientated concept of SystemVerilog, and can make use of other features as well like randomization, coverage, queues, semaphores, etc. Moreover it opens the door of reuse in the existing environment with the concept of OOPS and methodology.

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Verifying a CoFluent SystemC IP Model from a SystemVerilog UVM Testbench in Mentor Graphics Questa

The number of advanced features supported by multimedia devices is constantly growing. In order to support these functionalities, these devices require integrating numerous hardware Intellectual Property (IP) components, which drastically increase the global system complexity. Electronic System Level (ESL) methodology aims at raising the level of abstraction of the system description in order to address this outstanding complexity. Within the ESL ecosystem, early architecture exploration mainly relies on SystemC Transaction-Level Modeling (TLM) whereas SystemVerilog and Open/ Universal Verification Methodologies (OVM/UVM) are widely adopted by verification teams.

In this paper, we present a methodology that enables taking the best of both worlds, SystemC and SystemVerilog, by using OVM testbenches to verify SystemC IPs generated from functional models captured in a graphical language.

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What you need to know about dead-code and x-semantic checks

Dynamic simulation is essential for verifying the functionality of a design. In order for us to understand the progress of verification in a project, coverage is used as a measure of verification completeness. The coverage space for today’s designs is a multi-dimensional, orthogonal set of metrics [1]. This set includes both white-box metrics measuring the coverage inside the design and black-box metrics measuring the end-to-end behavior. White-box metrics are typically implementation-based, whereas black-box metrics are typically implementation-independent. For example, statement and condition coverage are examples of implicit white-box metric that can automatically be derived from the RTL model. In contrast, a scoreboard is an example of a higher-level explicit black-box metric that ignores the implementation detail of the design. A black-box metric can be used even when the design is represented at different levels of abstraction.

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