October 2012—Volume 8, ISSUE 2
“For verification, productivity really comes down to being able to reliably determine if your chip will run correctly as efficiently as possible.”
Tom Fitzpatrick, Editor and Verification Technologist
Oct 2012 Issue Articles
- ST-Ericsson Functional Verification Gains
- The Top Five Formal Verification Applications
- 3 Steps to Unified SoC Design & Verification
- The Evolution of UPF
- Improving Analog/Mixed-Signal Verification Productivity
- VHDL-2008 Why it Matters
ST-Ericsson Functional Verification Gains
Functional verification is one of the most critical steps in the IC development cycle. As complexity increases, along with the associated cost of fixing late-stage functional defects, manufacturers including ST-Ericsson are putting additional effort into the up-front verification process.
The Top Five Formal Verification Applications
It’s no secret. Silicon development teams are increasingly adopting formal verification to complement their verification flow in key areas. Formal verification statically analyzes a design’s behavior with respect to a given set of properties. Traditional formal verification comes in the form of model checking which requires hand-coded properties, along with design constraints. While there certainly are some design groups who continue to be successful with that approach, what are getting more widespread adoption in the industry are the automatic approaches which require much less manual setup. Let’s take a look at the top five applications being used across the industry today.
3 Steps to Unified SoC Design & Verification
The Mentor System Design and Verification flow reduces project risk, increases predictability, and improves verification productivity by allowing important system-level behavior, performance, and power to be validated early; allowing software to be developed in parallel with the hardware design; and enabling a consistent flow between SystemC and SystemVerilog/UVM using TLM 2.0 and UVM Connect as the enabling technology. Using software-driven verification of RTL at the block and subsystem levels allows early development and validation of drivers with the RTL. Although described here as a three step process, these steps are frequently overlapping and allow for an iterative process among the three main steps to resolve platform level issues.
The Evolution of UPF
Low power design is here to stay—it is a critical aspect of every chip design today. IEEE Standard 1801 UPF is the notation that enables low power design and verification in the context of a conventional HDL-based design flow. And just as design and implementation techniques continue to evolve over time, UPF is also continuing to improve over time, to meet the needs of design and verification engineers concerned with power management.
Improving Analog/Mixed-Signal Verification Productivity
Analog/Mixed-Signal design and verification is becoming a major challenge in SoC design and requires an increasing amount of dedicated and costly resources. Good engineering has a balance between top-down and bottom-up design approaches but there should generally be a bias towards top-down because the ultimate goal is to meet the system requirements since the balancing force is feasibility. A mixed-signal-on-top topology can be considered as a generalized approach that offers more flexibility than the other two topologies while allowing the user to meet the necessary requirements.
VHDL-2008 Why it Matters
VHDL-2008 brings new and enhanced features that increase reuse, capability, and productivity, and as a result, simplify coding and facilitate the creation of advanced verification environments.