Volume 10, Issue 1
Using Mentor Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged and tested.
Dealing With UVM and OVM Sequences
Because UVM/OVM are TLM-based, sequence and sequence items play vital roles and must be created in the most efficient way possible in order to reduce rework and simulation time, and to make the verification environment user friendly.
Don’t Forget the Little Things That Can Make Verification Easier
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable.
Stories of an AMS Verification Dude: Putting Stuff Together
I don't know how this came about, but the other day I got hired to do something called AMS Verification. It seems that there is this chip design that combines digital and analog stuff, and I was asked to make sure that all of it works when it's put together and that it does what it was meant to do when they got going in the first place.
Taming Power Aware Bugs with Questa
The internet revolution has changed the way we share content and the mobile revolution has boosted this phenomenon in terms of content creation & consumption. Moving forward, the Internet of Things would further drive this explosion of data.
Whether It's Fixing a Boiler, or Getting to Tapeout, It's Productivity that Matters
Being up against a tapeout deadline isn’t all that different from fixing a heating system before a winter storm hits. Although the stakes are different in these two scenarios, it’s ultimately productivity that matters.