Advanced Platform Architecture Package
Vista™ is an integrated TLM 2.0-based solution for architectural design exploration, verification, and virtual prototyping. Vista enables system architects and SoC designers to make viable architecture decisions, and it allows hardware and software engineers to validate their hardware and software early in the design cycle. This is accomplished by prototyping, debugging, and analyzing complex systems before the RTL stage, establishing a predictable and productive design process that leads to first-pass success. Learn more about the full portfolio of Vista solutions
Networking, storage systems, and multicore SoCs are rapidly becoming more complex, making architecture decisions increasingly critical and directly impacting competitive advantage. Critical tasks include configuring multicore hardware/software architectures and communication fabrics and ensuring that a system can carry its load and data traffic capacities.
Vista offers top-down modeling, a set of key architecture blocks that can be easily configured, an intuitive graphical assembly platform, and a hardware/software debug and analysis toolset.
The models constructing the system can be intuitively set to various micro-architecture configurations, interconnect layering, and memory hierarchies. The unique layered timing approach offered by Vista enables users to quickly test various configurations using powerful timing policies while keeping functionality intact. Users can scale and tune timing and power accuracy from high-level approximations down to the target bus and protocol. For efficient data tracing, users can utilize complex data objects (data packets), tag them with an ID, then trace and analyze their flow in the system.
Users can exercise statistical and randomized data traffic simulation or software-driven simulation with a target processor.
Vista has a powerful analysis toolset for intuitively viewing and analyzing different performance and power metrics, as well as for observing load peaks, average latencies, throughput, and utilization on any port, bus, or sub-system.
With Vista, users can rapidly prototype systems using the key hardware blocks and analyze power and performance under different scenarios and traffic loads. The scalable modeling approach supported in Vista enables design teams to manage timing and power from system concept to the desired implementation. This ensures that silicon is optimized, carries the data capacities for a given application, and scales to support future derivations of a product.
Features and Benefits
- Assess performance and power metrics early
- Minimize risks and maximize quality of results
- Manage and balance timing and power budgets from concept to implementation
- Understand the properties of the key scaling algorithms
- Use deterministic scalability
- Set of configurable TLM 2.0-based architecture blocks: CPU, BUS (AXI, AHB), Memory, Cache, DMAC, INTC, and others
- Statistical and functional up-front modeling utilities
- Tracing of data packets and model states and attributes
- TLM 2.0 graphical assembly
- Integrated HW/SW platform with target processors and SW tools
- Advanced SystemC and TLM 2.0 debug and tracing
- Advanced analysis and visualization tools and reports
- Analyze power, throughput, latencies, utilization, and states
Visual Elite™ is a state-of-the-art design and integration platform that enables designers and system architects to intuitively capture and connect SystemC, TLM 2.0, and HDL blocks into complex SoCs and systems.