Advanced TLM-RTL Design and Integration Platform
Visual Elite™ is the state-of-the-art design and integration platform enabling designers and system architects to intuitively capture and connect SystemC, TLM 2.0 and HDL blocks into complex SoC’s and systems.
Visual Elite is built upon a strong HDL implementation infrastructure while offering the most advanced electronic system-level (ESL) and transaction level modeling (TLM) concepts and mechanisms. Visual Elite greatly simplifies and accelerates capturing design structures in a hierarchical manner from untimed algorithmic systems and TLM architectures down to HDL descriptions. Delivering a design and integration platform across abstraction levels and domains is key to managing design complexities and disciplines throughout the design life-cycle.
Features and Benefits
- Continuous development process from TLM to RTL implementation
- Mix and match different levels of abstractions
- Native language front-end eases learning curve and adoption
- Intuitive design methods allow design sharing and reuse
- Improves revision control tracking and documentation
- Multi-discipline design management
- SystemC and HDL Mixed language design and integration
- Variety of text and graphical design creation methods
- Native SystemC and TLM 2.0 graphical assembly
- Cross language code generation
- Unique macro set for SystemC and HDL data flow design
- Automatically maps source code into graphical representation
- Seamlessly Integrates 3rd party models
- Link with Vista, Questa and other mixed language simulators
- Built in documentation
- Design life-cycle management platform
Vista™ is an integrated TLM 2.0-based solution for architectural design exploration, verification, and virtual prototyping. Vista enables system architects and SoC designers to make viable architecture decisions, and it allows hardware and software engineers to validate their hardware and software early in the design cycle. This is accomplished by prototyping, debugging, and analyzing complex systems before the RTL stage, establishing a predictable and productive design process that leads to first-pass success.
The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF