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Visualizer Debug Environment

High performance debug environment for digital design and verification

Intuitive and easy to use, Visualizer Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs.

Find bugs faster in the Visualizer Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa Simulation and Veloce Emulation, it provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Benefits and Features

  • High-performance, high-capacity debug environment available in interactive and post-sim modes
  • Unified debug support for both Questa Simulation and Veloce Emulation

Details

The Visualizer Debug Environment delivers:

  • TimeCone view and causality tracing, which automate tracing back to the source of an event and present the user with exactly what is needed to resolve the issue
  • Biometric advanced search capabilities to find and highlight events anywhere in the system, allowing you to focus your debug task
  • Complete set of SystemVerilog class, UVM-aware debug, assertion debug and synchronized transaction-level debugging
  • Waveforms and a dedicated transaction stripe viewer for testbench debug
  • Improve debug productivity for transaction, testbench, RTL, gate-level and low power design and verification
  • High-performance, high-capacity, available for both interactive and post-simulation
Fast Waveforms
TimeCone Tracing
UVM-Aware Debug
 
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