IC Manufacturing

Solutions for the GDSII-to-Mask Flow

Mentor delivers solutions tailored to your key challenges in the GDSII-to-Mask flow including maintaining tight critical dimension (CD) control for high wafer yield and reducing time-to-mask, cost of operation, and the duration and cost of new technology development.

The Mentor tool suite provides seamless integration of the data manipulations required for resolution enhancement (RET), such as phase shift mask (PSM), scattering bars (SB) and optical proximity correction (OPC), as well as mask rule checking, mask writer process correction, and data format conversion, all in a single batch run. Our solution is built on a common hierarchical database and geometry processing engine, which provides functions like layer derivation, mirroring, scaling, rotation, planarization fill, and global and selective sizing. The flow concludes with output in the most important mask writer formats for advanced mask-making in the subwavelength era, such as MEBES and Variable-Shaped-Beam (VSB) formats, as well as GDSII.

Leading-Edge Mask Enhancement and Fabrication

Over the last decade, we’ve helped dozens of fabs improve their mask quality and design-to-mask turnaround time (TAT) with a combination of:

Best-in-class technology
Flexible solutions that provide a wide choice of tool interfaces and hardware platforms
An engineering support team that works as a trusted partner and advisor to ensure your success

Integrated Design-to-Mask Virtual Manufacturing Flow

Layout physical and electrical verification
Design-For-Manufacturing (DFM) modeling and optimization
Comprehensive resolution enhancement techniques (RET)
State-of-the-art optical proximity correction (OPC) and verification
Dedicated mask writer process correction (MPC)
Hierarchical mask rule checking (MRC)
Mask fracturing and mask writer data conversion

Open and Accessible

All our tools are open and accessible through a variety of interfaces, allowing you to optimize your flow for the fastest tapeout-to-mask.

Calibre and Oasis database APIs
Lithography and metrology APIs
Common rule and control languages

IC Manufacturing Design Tools

Calibre® Computational Lithography

The Calibre computational lithography solution provides core innovations that ensure image fidelity across multiple process conditions, providing more robustness and reliability in the manufacturing process.

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WHITE PAPER: Convergence-based OPC Method for Dense Simulations

Calibre Mask Process Correction

The Calibre Mask Process Correction solution applies Mentor's model-based OPC technology with optimizations specifically developed for e-beam mask writers.

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WHITE PAPER: Improving the CD Linearity and Proximity Performance of Photomasks Written on the Sigma7500-II DUV Laser Writer Through Embedded OPC

Calibre Mask Data Preparation

Mentor's Mask Data Preparation (MDP) solution is fully compatible with the Calibre platform, enabling you to complete all resolution enhancement processing and mask data format conversion tasks in one mask fabrication batch run using a single control language.

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White Papers and Successes

IC Manufacturing White Papers

Calibre Pattern Matching: Picture It, Match It...Done!

White Paper: Calibre Pattern Matching is an extension to SVRF that simplifies complex rule checks required for advanced IC processes. This white paper discusses the conditions that have created the need for pattern... View White Paper

Computational Lithography, Scaling’s Best Friend

White Paper: Previously, scaling was enabled solely though changes in the physical domain, whether through decreasing the wavelength of light, increasing the numerical aperture, or producing chemically amplified resists.... View White Paper

Deployment of OASIS in the Semiconductor Industry – Status, Dependencies and Outlook

White Paper: The OASIS working group was first initiated in 2001, published the new format in March 2004, which was ratified as an official SEMI standard in September 2005. A follow-on initiative expanded the new standard... View White Paper

At the 2008 Design Automation Conference in June, Joseph Sawicki, vice president and general manager of the Design to Silicon Division, laid out Mentor’s strategy to help customers with the challenges they face with IC implementation as they move to smaller process nodes.

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Executive Brief: Meeting the Critical Challenges of IC ImplementationOn-demand Web Seminar