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IC Manufacturing Blog

21 Mar, 2014

I See the Light!

Posted by Shelly Stalnaker

Shelly Stalnaker Photonics technology isn’t new, by any means, but what is new is the drive to leverage high-volume silicon-based semiconductor manufacturing foundries and processes to build chips that can create, sense, modulate, and transmit light. So says Michael White in his latest SiliconEdge column on Electronic Design. The biggest challenge in applying CMOS foundry processes to silicon photonics is creating … Read More

Foundry, IC Design, silicon photonics, waveguides, ic manufacturing, Michael White

14 Mar, 2014

Are You ECO-Friendly?

Posted by Shelly Stalnaker

Shelly Stalnaker Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor … Read More

P&R, Jeff Wilson, place and route, 45nm, 20nm, IC Design, smart fill, ic manufacturing, DRC, ECO fill

3 Mar, 2014

EUV...Ready or Not?

Posted by Shelly Stalnaker

Shelly Stalnaker The semiconductor industry can (and does) argue about when extreme ultraviolet lithography will be ready for production. However, the actual dates are irrelevant to those engineers who must prepare OPC tools and processes for the EUV-specific effects that will have to be managed in manufacturing. They are busy now, evaluating the impact of such challenges as the distortion caused by EUV shadowing. In … Read More

SRAF, scanner, EUV shadowing, extreme ultraviolet, EUV, mask, OPC, ic manufacturing, Lithography

3 Mar, 2014

Lights! Camera! Multi-Patterning!

Posted by Shelly Stalnaker

Shelly Stalnaker David Abercrombie recently met with Brian Bailey of Semiconductor Engineering to explain many of the concepts and issues of multi-patterning that he has been writing about for the last couple of years. If you want to understand the basics of multi-patterning requirements, 12 minutes is all you need to check out their first video: Tech Talk: Multipatterning on semiengineering.com. If the video piques … Read More

double patterning, EUV, 20nm, Multi-Patterning, triple patterning, IC Design, ic manufacturing

13 Feb, 2014

I SPIE, with my little eye...

Posted by Shelly Stalnaker

Shelly Stalnaker Are you attending the SPIE Advanced Lithography conference beginning Feb 23rd? If so, you’ll want to take note of the following Mentor presentations…there’s something for everyone. For detailed abstracts, go to the SPIE Technical Summaries document. Feb 25, 4:40pm: Feasibility of compensating for EUV field edge effects through OPC Feb 25, 5:20pm: Pattern fidelity verification for logic design in EUV … Read More

29 Jan, 2014

UPDATE: Multi-Patterning Unmasked!!

Posted by Shelly Stalnaker

Shelly Stalnaker Download the latest version of our guide to multi-patterning design and debugging, containing links to all of David Abercrombie’s detailed educational articles on SemiEngineering.com, along with links for complementary reference and learning options. Whether you are already working on designs with multi-patterning requirements, or just beginning multi-patterning work, you will benefit from David’s … Read More

triple patterning, double patterning, IC Design, Debugging, Physical Verification, SADP, ic manufacturing, Multi-Patterning

21 Jan, 2014

Shelly Stalnaker Foundries, both pure-play and independent device manufacturers (IDM), rigorously compete for market share. One factor that helps them get and keep business is turnaround time (TAT). Until recently, companies could reduce TAT by adding computer hardware, fine-tuning OPC recipes, improving input hierarchical handling of designs, and upgrading to new software versions with new functionality and performance … Read More

cluster management, Fabless, Calibre CalCM, resource management, turnaround time, Foundry, ic manufacturing

 
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