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Are You ECO-Friendly?

Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor Manufacturing & Design, Jeff Wilson explains how an effective ECO fill strategy can help reduce runtime, manage file size, and minimize timing impacts.

P&R, Jeff Wilson, place and route, 45nm, 20nm, IC Design, smart fill, ic manufacturing, DRC, ECO fill

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About Shelly Stalnaker

Shelly StalnakerI believe in the well-written sentence, the eye-catching title, and the satisfaction of hearing someone say, “Now I get it.” I believe there ought to be a constitutional amendment outlawing the use of the passive tense in technical writing. I believe a writer can explain and entertain at the same time, and I believe that everyone, even in the business world, has a story to tell. Visit Foundry Solutions

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