A new publication on mechanical stress in ICs, co-edited by Valeriy Sukharev, Principal Engineer for Calibre R&D, has just been released by AIP Publishing. Stress-Induced Phenomena and Reliability in 3D Microelectronics includes papers from international workshops held in the U.S., Germany, and Japan. Management of mechanical stress is one of the key enablers for the successful implementation of 3D-ICs using through-silicon vias (TSVs). The potential stress-related impact of the 3D integration process on product reliability must be understood, and designers need solutions for identifying and managing stress effects.
The papers focus on Design-for-Reliability (DFR), and propose a stress management simulation flow that enables designers to model stress implications on their designs quantitatively. The papers also discuss multi-scale modelling and simulation, multi-scale materials parameters, and multi-scale analysis. Development of 3D-IC integration strategies provides a potential solution for overcoming the wiring limit imposed on interconnect density, performance, and power consumption of integrated circuits.
To order your copy of this AIP publication, click here. And chillax…stress is bad for people, too!