Calibre Computational Lithography
Low k1 photolithography processes are driving up the complexity and data volume of RET applications in nanometer designs. At 45nm and beyond, more complex models and through-process-window correction and verification requirements significantly increase computational burden. Both the lithographic challenges and the computational complexity associated with the advanced process nodes create a need for advanced capabilities in computational lithography software and hardware.
The Calibre® computational lithography solution answers these challenges with core innovations that ensure image fidelity across multiple process conditions, providing more robustness and reliability in the manufacturing process.
The Calibre solution offers best-in-class accuracy, speed, and cost of ownership. Streamlined hierarchical processing enables Calibre to take advantage of design hierarchy to improve turnaround time, computational efficiency, and throughput compared to flat processing tools. Hardware co-processor acceleration support, based on the powerful multicore Cell/B.E. numerical processor, reduces turnaround time even further, while reducing the total cost of computing.
High-performance Resolution Enhancement Technology for advanced IC manufacturing processes.
Virtual manufacturing solution supports RET recipe optimization.
Full-chip correction increases yield and process latitude.
Solution for accurate tool setup - Calibre WORKbench
Full support for adding, simulating and verifying scattering bars.
- Calibre TDopc™
Calibre TDopc provides Table-Driven OPC functionality via two Calibre commands:
- OPCBIAS makes it easy to do fast rule-based OPC for line widths based on a simple table of values.
- OPCLINEEND makes it easy to apply line end treatments, such as hammerheads, based on a simple table of values.
- Calibre PRINTimage™
Calibre PRINTimage produces a full-chip, batch output of simulated silicon shapes, and enables simplified DRC checks on these shapes, so-called “silicon DRC.” Simulation is based on optical and process model developed from measured manufacturing process characteristics. The simulator handles PSM effects, including attenuated PSM side lobe detection and strong PSM phase imbalances. Calibre PRINTimage outputs the simulated silicon shapes in a new GDSII output layer.
- Calibre LITHOview™
Calibre LITHOview is a subset of Calibre WORKbench for users who need to confirm layout or OPC model results but do not generate new models. It offers all the capabilities as WORKbench, except model creation and test pattern generation.
- Calibre ORC™
Calibre ORC (Optical and Process Rule Checking) provides full-chip batch checking for IC manufacturing "printability" problems, called EPEs (Edge Placement Errors). Calibre ORC uses a calibrated optical and process model developed from manufacturing process characteristics. Calibre ORC predicts the silicon location 1D and 2D structures of interest in the design (e.g. line ends, corners, or user-defined structures). If the EPE for that type of structure is greater than a user-set tolerance, Calibre ORC creates a viewable "error box" over the edge in a new GDSII output layer, as well as summary reports including statistics. Calibre ORC integrates with popular layout editors via the Calibre RVE™ (results viewing environment), enabling easy viewing and debugging.
- Calibre PSMgate™
Calibre PSMgate provides full-chip, batch phase assignment to increase yield and chip speed for subwavelength lithography using existing manufacturing equipment. Calibre PSMgate makes changes to the layout to enable significantly smaller gate features than the wavelength of the light used in manufacturing. Calibre PSMgate uses Calibre OPCpro “phase-aware" model-based OPC algorithms to correct phase distortions typically found near phase transitions and line ends. Some of the Calibre PSMgate key features include:
- Many types of PSM techniques can be both assigned and verified, such as one-/two-exposure and two-/three-/four-phase methods.
- Although primarily used for one-half to one-third wavelength sized gates today, the assignment algorithm can be applied to other selected layers/structures as well.
- Can be used for full layer PSM, including critical interconnects around gates.
- Works with Calibre layout processing engine to provide layer derivations, Boolean operations, and phase-conflict checking essential to a strong or attenuated complete PSM flow.
- Supports shape-based checking, long-range “color ability” and side-lobe detection and correction.
Please contact us at:
firstname.lastname@example.org or call 800-547-3000 if you are interested in, or would like more information about the products above.