Current low k1 photolithography processes are increasing the complexity of resolution enhancement technology (RET) applications in nanometer designs. This has resulted in higher silicon failure rates caused by mask rule constraints, fragmentation, modeling and metrology errors, and more. To reduce errors, a post-OPC verification step is needed to detect failures before a design is sent to the mask or wafer manufacturer.
Features and Benefits
- Accurate wafer contour simulation for advanced process conditions, including immersion litho
- Supports a variety of OPC usage models, including OPC recipe verification, mask sign-off, litho-friendly design, VT5 and optical
- Predefined and customizable scripts for CD errors, spacing errors, bridging and pinching checks, and two-layer checks
- Easily customized and integrated into existing flows
- Calibre hierarchical polygon processing engine provides a single, accurate modeling foundation for all litho simulations
- High processing scalability assures necessary turn-around-time for mask operations
- No dedicated hardware; runs on all leading platforms
High-performance Resolution Enhancement Technology for advanced IC manufacturing processes.