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News Article:Mentor Graphics and JEOL to Develop Advanced IC Mask Writing Solutions

Wed, 23 Nov 2011 14:00:00 GMT

WILSONVILLE, Ore., November 23, 2011—Mentor Graphics Corporation (NASDAQ: MENT) and JEOL Ltd. today announced an agreement to collaborate on integrated hardware and software solutions for advanced IC mask writing. The companies are currently engaged in a research program to demonstrate the feasibility of an innovation called multi-resolution writing for shot count reduction of up to 30% compared to the conventional writing technique, dramatically reducing mask writing time. The new agreement is focused on developing this technology as well as providing optimized interfaces between the Mentor® mask data preparation and mask process correction (MPC) software and JEOL e-beam lithography equipment.

White Paper:Patterning Process Models Presentation

Fri, 05 Aug 2011 07:00:00 GMT

This presentation reviews the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools down to 14 nm node, as well as the factors that ultimately limit the predictability of such models. It also outlines the new process simulation challenges that emerge as the industry approaches sub-0.25 k1 patterning: improving accuracy and predictability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

White Paper:Challenges for Patterning Process Models Applied to Large Scale

Fri, 05 Aug 2011 07:00:00 GMT

Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasi-rigorous optical models and semi-empirical resist and etch process models. This paper will review the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools, as well as the factors that ultimately limit the predictability of such models. In addition, this paper will outline the new process simulation challenges that emerge as the industry approaches sub-0.25 k1 patterning: improving accuracy and predictability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

News Article:Mentor Graphics and GLOBALFOUNDRIES Extend RET and OPC Collaboration to 28nm

Tue, 01 Mar 2011 14:00:00 GMT

WILSONVILLE, Ore., March 1, 2011—Mentor Graphics Corporation (NASDAQ: MENT) and GLOBALFOUNDRIES today announced that the companies have extended their collaboration on computational lithography to the 28nm technology node. Building on a successful deployment at 65nm and 45nm, GLOBALFOUNDRIES will leverage Mentor’s Calibre® computational lithography platform to support its advanced mask production needs at 28nm. The announcement underscores the two companies’ commitment to collaboration in order to deliver enablement technology for advanced nodes.

News Article:New Shanghai HuaLi Foundry Chooses the Mentor Graphics Calibre RET Solution for 65/45nm Development and Production

Mon, 28 Feb 2011 14:00:00 GMT

WILSONVILLE, Ore., February 28, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced that Shanghai HuaLi Microelectronics Corp., a joint foundry venture of the China Government, Shanghai Alliance Investment Co., Ltd, Shanghai Hua Hong (Group) Co., Shanghai Grace Semiconductor Manufacturing Corp., and Shanghai Hua Hong NEC Electronics Co., Ltd, has chosen the Calibre® RET and OPC Computational Lithography platform to support its 65, 55 and 45nm development and production. The Mentor® Calibre nmOPC and Calibre OPCverify™ products were selected following a comprehensive technical benchmark in which the Calibre solution demonstrated superior accuracy, ease of use, cost of ownership and overall support capability.

Technology Overview:Safety Critical Design Solutions

Wed, 08 Dec 2010 21:06:00 GMT

In this session, Jim Henson, Product Marketing Manager at Mentor Graphics discusses IEC 61508, "Functional safety of electrical/electronic/programmable electronic safety-related systems." This standard is a product oriented (hardware/software) functional safety standard created by the International Electrotechnical Commission (IEC). A robotics control system manufacturer using programmable FPGA devices for safety logic is required to comply with IEC61508 in order to deliver to an EU customer. Mentor's FormalPro Equivalence Check tool is used to prove that the final FPGA netlist is equivalent to the design-level RTL which satisfies the safety requirement..

White Paper:Improved Process Window Modeling Techniques

Tue, 19 Oct 2010 07:00:00 GMT

The continuous reduction of device dimensions and densities of integrated circuits increases the demand for accurate process window models used in optical proximity correction. Beam focus and dose are process parameters that have significant contribution to the overall critical feature dimension error budget. The increased number of process conditions adds to the model calibration time since a new optical model needs to be generated for each focus condition. This study shows how several techniques can reduce the calibration time by appropriate selection of process conditions and features while maintaining good accuracy. Experimental data is used to calibrate models using a reduced set of data. The resulting model is compared with the model calibrated using the full set of data. The results show that using a reduced set of process conditions and using process sensitive features can yield a model as accurate as the model calibrated using the full set but in a shorter amount of time.

White Paper:Contour-Based Self-Aligning Calibration of OPC Models

Tue, 19 Oct 2010 07:00:00 GMT

SEM contours are used to complement CD measurements in OPC model calibration. This is done to capture 2D information about printed features into the model while CD measurement data is kept to maintain accuracy for 1D features. As the method progresses, there are emerging challenges that are normally not found in CD based calibration. One such challenge is the need to align SEM contours with calibration features. This is particularly important in determining model accuracy since contour calibration typically involves a cost function that compares the SEM contours to the simulated print images.

This work explores a technique to include contour alignment errors into the calibration cost function. For each contour and its corresponding simulated print, the cost function returns an error value for a given set of model parameters. The error represents how well the model simulation compared to input contour. In addition, it also contains information on how far or how close the contour is aligned to simulation. Misalignment is to be eliminated on the fly during calibration and to be reported at the end of calibration.

In this paper we describe the proposed technique and compare the results of calibration between aligned and misaligned contour data.

White Paper:Device Performances Analysis of Standard-Cells Transistors using Silicon Simulation and Build-in Device Simulation

Tue, 19 Oct 2010 07:00:00 GMT

A simple methodology to predict transistors performances due to systematic lithography and etch effects is presented. It is based on physical silicon simulation, followed by device modeling, incorporated in the silicon simulation software. This method enables an easy and efficient analysis of device parameters with the same simulation tool usually used for process analysis. The method is demonstrated on small and large arrays of standard cell blocks, designed for TS013SL (0.13µm Standard Logic for General Purposes) Platform. Electrical parameters, like drive current (Idsat), and Off current (Ioff) were predicted. Comparison between different transistors types, having the same W/L but different layout configuration and various layout environments (around the transistor) was made in terms of performances as well as process variability.

White Paper:OPC Recipe Optimization Using Simulated Annealing

Thu, 14 Oct 2010 07:00:00 GMT

One of the major problems in the RET flow is OPC recipe creation. The existence of numerous parameters to tune and the interdependence between them complicates the process of recipe optimization and makes it very tedious. There is usually no standard methodology to choose the initial values for the recipe settings or to determine stable regions of operation. In fact, parameters are usually optimized independently or chosen to resolve a certain issue for a specific design without quantifying its effect on the quality of the recipe or how it might affect other designs. Another problem arises when a quick fix is needed for an old recipe to build new design masks, and this causes the stacking of many customization statements in the OPC recipe, which in turns increases its complexity. Consequently, the experience of the developer is highly required to build a good as well as a stable recipe. In this context, simulated annealing is proposed to optimize OPC recipes. It will be shown how many parameters can be optimized simultaneously and how we can get insight about the stability of the recipe.