Executive Brief: Meeting the Critical Challenges of IC Implementation
On-demand Web Seminar
At the 2008 Design Automation Conference in June, Joseph Sawicki, vice president and general manager of the Design to Silicon Division, laid out Mentor’s strategy to help customers with the challenges they face with IC implementation as they move to smaller process nodes. Sawicki discusses new technology acquisitions and developments, product enhancements, and organizational alignment. He also describes how Mentor is driving toward the integration of its industry-leading IC implementation platforms based on a common vision for delivering first-pass silicon success.
What You Will Learn
You will learn about the evolution of Mentor’s comprehensive Design-to-Silicon IC implementation solution which consists of industry leading platforms for place-and-route, physical verification, Design-For-Manufacturing, Design-for-Test and yield improvement. This presentation discusses new capabilities including:
- Equation-based DRC for advanced multi-dimensional (2D/3D) physical verification (PV) checks that are difficult or impossible to perform today.
- Incremental verification features that allow multiple design rule checking runs to execute in parallel.
- Distributed computing enhancements to reduce memory requirements while improving runtime for Calibre nmDRC.
- Mentor’s new DFM planarity solution that optimizes metal fill for best performance using both CMP models and layout density analysis.
- New interactive debugging features for Calibre nmLVS to speed layout-versus-schematic checking.
Who Should View
Designers, managers and executives planning their technology roadmap to address the challenges of IC implementation at 45nm and beyond.
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