Industry Articles
April 2013
Cutting the Key to 14nm Lithography
January 2010
Weighing the Design Requirements for 22nm Lithography
Taming the runaway computational demands of advanced lithography
December 2008
Connecting design and fabrication
November 2008
Interview with J. Sturtevant: Computational Lithography
Manufacturable Source Mask Optimization
September 2008
Computational Lithography Technology Trends for 32nm
August 2008
TSMC Adopts Mentor Graphics Eldo Analog Simulation Tool - EDA Geek News
Accelerating Both Sparse and Dense OPC Simulation
May 2008
April 2008
Etch's Role in Novel Logic Device Patterning
February 2008
IBM Qualifies Mentor's 45-nm tools
Embedded OPC Extends Laser Mask Writers to 65/45nm
January 2008
Doubling Down: Design-Side Issues of Double Patterning
September 2007
Enabling Yield at 45nm: Managing Process Variability
August 2007
Importance of Silicon Validation
May 2005
Guidelines to Maximize the Performance of Verilog-AMS/VHDL-AMS Behavioral Modeling
April 2005
February 2005
Litho H2O: OPC Modeling for Immersion Lithography
April 2004
Design for Manufacturing Must Move up in the IC Flow
March 2004
Silicon Modeling in the Nanometer Era
A New Definition of Fracturing
January 2004
Design-for-manufacturing demands new infrastructure
GDSII-based flow speeds mask data preparation
September 2003
A Little Light Magic, IEEE Spectrum
July 2003
The Glue In A Confident SoC Flow
Turning Up The Yield - IEE Electronics Systems and Software
December 2002
Mixed-signal design flow enables RF CMOS chip
Another way around monster mask costs
November 2002
August 2002
Mentor Unveils Big Mixed Signal Play
The Future of Extraction in Mixed-Signal Design
July 2002
Solutions for Maximizing Die Yield at 0.13 Micron - Solid State Technology
The Power of One: Eliminating the Problems of Dual Physical Verification Flows
June 2002
What designers should know about RET
April 2002
Single tool serves IC verification best
January 2002
Choosing a Fast, Smart and Accurate LVS Tool
December 2001
September 2001
Simulation Tool Models And Verifies Timing Jiter In Oscillators - MICROWAVES & RF
Optimal insertion points for OPC and PSM in design flows
April 2001
Technique will change chip design, speakers say
March 2001
Panel debates value of mixed-signal design tools
February 2000
ASML Masktools offers scattering-bar IP for use with Mentor Graphics' Calibre software
IC Manufacturing Press Releases
- Mentor Graphics and JEOL to Develop Advanced IC Mask Writing Solutions (Nov 23, 2011)
- Mentor Graphics and GLOBALFOUNDRIES Extend RET and OPC Collaboration to 28nm (Mar 1, 2011)
- New Shanghai HuaLi Foundry Chooses the Mentor Graphics Calibre RET Solution for 65/45nm Development and Production (Feb 28, 2011)
- Mentor Graphics Design-to-Silicon Solutions Implemented as Part of Samsung Electronics’ New 32nm High-K Metal Gate Offering (Jun 11, 2010)
- Freescale Semiconductor Collaborates with Mentor Graphics on Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM (Jan 11, 2010)
- GLOBALFOUNDRIES Selects Mentor Graphics Calibre Platform for Computational Lithography and DFM Enablement (Oct 16, 2009)
- Mentor Graphics and Applied Materials Deploy OASIS.MASK Open Data Standard for Higher Efficiency Mask Manufacturing (Sep 14, 2009)
- Mentor Graphics Eldo Simulator used by STMicroelectronics to Characterize 32nm Cell Libraries (Mar 5, 2009)
- Mentor Graphics Olympus P&R and Calibre Verification Platforms Qualified for 32nm IC Designs at STMicroelectronics (Mar 2, 2009)
- Selete Selects Mentor Graphics Calibre nm Platform for EUV Flare Compensation (Feb 27, 2009)